ROD firmware  1.0.5
ATLAS l1-calo - ROD_eFEX and ROD_jFEX firmware for the L1Calo ROD board

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ev_builder.vhd
1 
3 
4 ----------------------------------------------------------------------------------
5 -- Company: University of Cambridge
6 -- Engineer: Ed Flaherty
7 --
8 -- Create Date: 10.02.2017 11:53:28
9 -- Design Name: L1Calo ROD
10 -- Module Name: ev_builder - RTL
11 -- Project Name: L1Calo phase-I upgrade
12 -- Target Devices:
13 -- Tool Versions:
14 -- Description:
15 --
16 -- Dependencies:
17 --
18 -- Revision:
19 -- Revision 0.01 - File Created
20 -- Additional Comments:
21 --
22 ----------------------------------------------------------------------------------
23 
24 
25 library IEEE;
26 use IEEE.STD_LOGIC_1164.ALL;
27 
28 -- Uncomment the following library declaration if using
29 -- arithmetic functions with Signed or Unsigned values
30 use IEEE.NUMERIC_STD.ALL;
31 use IEEE.STD_LOGIC_UNSIGNED.ALL;
32 use work.controller_codes.all;
33 use work.ff.all;
34 -- Uncomment the following library declaration if instantiating
35 -- any Xilinx leaf cells in this code.
36 --library UNISIM;
37 --use UNISIM.VComponents.all;
38 
39 
40 -----------------------------------------------------------------------------------
41 --This design will eventually support 12 input channels and 4 event building queues
42 --
43 --
44 -- signal definitions
45 --
46 ------------------INPUTS & OUTPUTS-------------------------
47 -- nxt_chan:........Increment the counter/pointer in the mux
48 -- chan_enable .....Originates at the channel control register, and is passed through the input mux
49 -- header_fifo_valid:........TTC fifo has a valid output
50 -- empty_n:.........inputs from other queues to say they are empty - used to determine highest priority empty queue
51 -- empty_stat:......output from this queue to indicate it is empty (or at a low level) and can start another event
52 -- match_n:.........inputs from other queues to indicate whether they are already working on a newly selected channel header
53 -- hdr_match:.......match output from this queue to be connected to match inputs on other queues.
54 -- poll_chan:.......set high for at least one cycle to read the data from the input buffer to the builder queue
55 -- current_chan.....4-bit binary output from the mux to indicate which channel is currently selected
56 
57 ---------------INTERNAL SIGNALS----------------------
58 -- header_marker....sideband signal from input fifo, active on first word (header) of an event fragment
59 -- tail_marker......sideband signal from input fifo, active on last word (tail) of an event fragment
60 -- hp_empty.........indicates that this queue is the highest priority queue that is ready to take a new header and event data
61 -- no_other_match...indicates that no other queue us already working on a newly selected channel
62 -- hdr_reg_valid....register indicating that the value in the header register is valid
63 -- header_reg.......the event header is loaded in this register so that the same header can be searched for in other channels
64 -- last_chan........indicates that the data is being taken from the last channel to be polled. necessary because you don't
65 -- know which channel the data will have been found in first
66 -- empty_out........replaced by empty_stat
67 -- poll.............pulse high one cycle to start the packet write from input buffer to event queue
68 -- inc_chan.........pulse high one cycle to look at the next channel.
69 
70 
71 
72 
73 -- basic algorithm
74 --
75 --if the fifo is empty (or below some tbd threshold),
76 -- check that this is the highest priority empty queue and
77 -- check that no other queue already has a header match
78 -- if the above is true, then take owernership of this header
79 -- load into header register
80 -- set hdr_match
81 -- clear empty output
82 -- pulse the handshake, allow to write until trailer marker
83 -- increment to next input channel
84 
85 
86 entity ev_builder is
87  generic (
88  CRC20_G_Poly : std_logic_vector(19 downto 0) := x"8349f"; --old poly
89  jfex : integer := 0;
90  bp_width : integer := 64;
91  event_width : integer := 64;
92  header_width : integer := 64
93  );
94 
95  Port ( clock : in STD_LOGIC;
96  reset : in STD_LOGIC;
97  geo_location : in STD_LOGIC_VECTOR (7 downto 0);
98  s_tdata : in STD_LOGIC_VECTOR (bp_width-1 downto 0);
99  s_tvalid : in STD_LOGIC;
100  s_tlast : in STD_LOGIC;
101  s_header_mark : in STD_LOGIC;
102  s_trailer_mark : in STD_LOGIC;
103  s_hdr_crc_tag : in STD_LOGIC;
104  s_tready : out STD_LOGIC;
105  nxt_chan : out STD_LOGIC;
106  empty_0 : in STD_LOGIC;
107  empty_1 : in STD_LOGIC;
108  empty_2 : in STD_LOGIC;
109  empty_3 : in STD_LOGIC;
110  -- empty_stat : out STD_LOGIC;
111  match_0 : in STD_LOGIC;
112  match_1 : in STD_LOGIC;
113  match_2 : in STD_LOGIC;
114  match_3 : in STD_LOGIC;
115 
116 
117 
118  lead_follow_b : in STD_LOGIC;
119  comb_error : in STD_LOGIC;
120 
121  hdr_match : out STD_LOGIC;
122  poll_chan : out STD_LOGIC;
123 
124 
125  current_chan : in STD_LOGIC_VECTOR (4 downto 0);
126  num_chan : in STD_LOGIC_VECTOR (4 downto 0);
127  chan_in : in STD_LOGIC_VECTOR (4 downto 0);
128 
129 --channel enable from mux (chan_enable indicates that the channel is (UP AND not Disabled))
130  chan_enable : in STD_LOGIC;
131 
132 
133  first_chan : in STD_LOGIC_VECTOR (4 downto 0);
134  last_chan : in STD_LOGIC_VECTOR (4 downto 0);
135 
136  chan_pointer_reset : out STD_LOGIC;
137  any_chan_active : in std_logic;
138 
139  event_sel : in STD_LOGIC_VECTOR (1 downto 0);
140  rod_slot : in std_logic;
141  flx_backpressure : in STD_LOGIC;
142  flx_bp_enable : in STD_LOGIC;
143 
144 --TTC_ignore allows input packets to be processes as normal, even if the input header L1ID does not match the master header L1ID
145  --TTC_ignore input is temporarily deleted to allow it to be controlled by a vio in this block
146  TTC_ignore : in STD_LOGIC;
147 
148 
149 --TTC header input
150  master_header : in STD_LOGIC_VECTOR (63 downto 0); --synchronous to pp_clk
151  header_fifo_empty : in STD_LOGIC;
152  L1ID_error : in STD_LOGIC;
153  CTTC_CRC_error : in STD_LOGIC;
154  header_read_en : out STD_LOGIC;
155  header_fifo_valid : in STD_LOGIC;
156  header_fifo_full : in STD_LOGIC;
157  header_sequence : in STD_LOGIC_VECTOR (11 downto 0);
158  header_type : in STD_LOGIC_VECTOR (3 downto 0);
159 
160 
161 
162 --event output
163 
164  m_tvalid : out STD_LOGIC;
165  m_tlast : out STD_LOGIC;
166  m_tdata : out STD_LOGIC_VECTOR ((bp_width-1) downto 0);
167  m_header_marker : out STD_LOGIC;
168  m_tail_marker : out STD_LOGIC;
169  m_tready : in STD_LOGIC;
170 
171  state_out : out STD_LOGIC_VECTOR(5 DOWNTO 0);
172  event_fifo_level : out STD_LOGIC_VECTOR(31 DOWNTO 0);
173  debug_fifo_level : out STD_LOGIC_VECTOR(31 DOWNTO 0);
174 
175  crc20_err : out STD_LOGIC;
176  crc20_err_chan : out STD_LOGIC_VECTOR (4 downto 0) := "00000";
177  crc9_err : out STD_LOGIC;
178  BCID_mismatch : out STD_LOGIC; --1 cycle pulse: used for counting
179  l1ID_mismatch : out STD_LOGIC; --1 cycle pulse: used for counting
180  timeout_err : out STD_LOGIC; --1 cycle pulse:
181  timeout_1_val : in STD_LOGIC_VECTOR (15 downto 0);
182  timeout_n_val : in STD_LOGIC_VECTOR (15 downto 0);
183  wdog_overflow : out STD_LOGIC;
184  wdog_threshold : in STD_LOGIC_VECTOR (15 downto 0);
185  wdog_disable : in STD_LOGIC;
186  l1id_resync_enable: in STD_LOGIC;
187  tob_timeout_1_disable : in STD_LOGIC;
188  tob_timeout_n_disable : in STD_LOGIC;
189  ttc_rollover : out std_logic;
190  dbg_pkt_count : out std_logic_VECTOR (31 downto 0);
191  dbg_pkt_count_reset : in STD_LOGIC;
192  L1ID_ttc_32_reg_out : out std_logic_VECTOR (31 downto 0);
193  stop_proc : in std_logic;
194 
195  l1id_max_l1id_o : out std_logic_VECTOR (31 downto 0);
196  l1id_measure_max_o : out std_logic_VECTOR (31 downto 0);
197  l1id_measure_last_o : out std_logic_VECTOR (31 downto 0);
198  clr_pkt_wait_timer : in STD_LOGIC;
199 
200  -- timeout_counter_last : out STD_LOGIC_VECTOR(15 downto 0);
201  timeout_counter_max : out std_logic_VECTOR (15 downto 0);
202  max_chan : out std_logic_VECTOR (4 downto 0);
203  clr_max_timeout : in STD_LOGIC
204  );
205 
206 end ev_builder;
207 
208 architecture RTL of ev_builder is
209 
210 component event_builder_fifo
211  Port ( s_axis_tvalid : in STD_LOGIC;
212  s_axis_tready : out STD_LOGIC;
213  s_axis_aresetn : in STD_LOGIC;
214  s_axis_aclk : in STD_LOGIC;
215  s_axis_tlast : in STD_LOGIC;
216  s_axis_tuser : in STD_LOGIC_VECTOR (1 downto 0);
217  s_axis_tdata : in STD_LOGIC_VECTOR ((event_width-1) downto 0);
218 
219  m_axis_tvalid : out STD_LOGIC;
220  m_axis_tready : in STD_LOGIC;
221  m_axis_tlast : out STD_LOGIC;
222  m_axis_tuser : out STD_LOGIC_VECTOR (1 downto 0);
223  m_axis_tdata : out STD_LOGIC_VECTOR ((event_width-1) downto 0);
224 
225 -- axis_data_count : out STD_LOGIC_VECTOR (31 downto 0);
226  axis_wr_data_count : out STD_LOGIC_VECTOR (31 downto 0);
227  axis_rd_data_count : out STD_LOGIC_VECTOR (31 downto 0)
228 
229  );
230 end component;
231 
232 
233 
234 
235 
236 COMPONENT event_fifo_ila
237 
238 PORT (
239  clk : IN STD_LOGIC;
240 
241 
242 
243  probe0 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
244  probe1 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
245  probe2 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
246  probe3 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
247  probe4 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
248  probe5 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
249  probe6 : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
250  probe7 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
251  probe8 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
252  probe9 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
253  probe10 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
254  probe11 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
255  probe12 : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
256  probe13 : IN STD_LOGIC_VECTOR(5 DOWNTO 0)
257 );
258 END COMPONENT ;
259 
260 COMPONENT ILA_ev_builder
261 
262 PORT (
263  clk : IN STD_LOGIC;
264 
265 
266 
267  probe0 : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
268  probe1 : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
269  probe2 : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
270  probe3 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
271  probe4 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
272  probe5 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
273  probe6 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
274  probe7 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
275  probe8 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
276  probe9 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
277  probe10 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
278  probe11 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
279  probe12 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
280  probe13 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
281  probe14 : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
282  probe15 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
283  probe16 : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
284  probe17 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
285  probe18 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
286  probe19 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
287  probe20 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
288  probe21 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
289  probe22 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
290  probe23 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
291  probe24 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
292  probe25 : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
293  probe26 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
294  probe27 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
295  probe28 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
296  probe29 : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
297 
298 );
299 END COMPONENT ;
300 
301 COMPONENT rx_time_ila
302 
303 PORT (
304  clk : IN STD_LOGIC;
305 
306 
307 
308  probe0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
309  probe1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
310  probe2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
311  probe3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
312  probe4 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
313  probe5 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
314  probe6 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
315  probe7 : IN STD_LOGIC_VECTOR(0 DOWNTO 0)
316 );
317 END COMPONENT ;
318 
319 component header_fifo
320  Port ( clk : in STD_LOGIC;
321  srst : in STD_LOGIC;
322  din : in STD_LOGIC_VECTOR ((header_width-1) downto 0);
323  wr_en : in STD_LOGIC;
324  rd_en : in STD_LOGIC;
325  full : out STD_LOGIC;
326  empty : out STD_LOGIC;
327  dout : out STD_LOGIC_VECTOR ((header_width-1) downto 0)
328  );
329 end component;
330 
331 component hdr_in_crc9 is
332  Port (
333  clock : in STD_LOGIC;
334  crc_reset : in STD_LOGIC; --connect to ld_hdr_reg in this level
335  s_tdata : in STD_LOGIC_VECTOR (63 downto 0);
336  crc_start : in STD_LOGIC; --connect to poll in this level
337  header_mismatch : out std_logic
338  );
339 end component;
340 
341 component event_hdr_crc9 is
342  Port (
343  clock : in STD_LOGIC;
344  crc_reset : in STD_LOGIC; --connect to hdr_sel_2 in the level above
345  BCN : in STD_LOGIC_VECTOR (11 downto 0);
346  version : in STD_LOGIC_VECTOR (2 downto 0);
347  tob_stream_id : in STD_LOGIC_VECTOR (7 downto 0);
348  ECRID : in STD_LOGIC_VECTOR (7 downto 0);
349  L1ID : in STD_LOGIC_VECTOR (23 downto 0);
350 -- header_reg_0 : in STD_LOGIC_VECTOR (31 downto 0);
351  header_reg_1 : in STD_LOGIC_VECTOR (31 downto 0);
352  header_reg_2 : in STD_LOGIC_VECTOR (31 downto 0);
353  crc_start : in STD_LOGIC; --connect to (hdr_out_crc9_start and ttc_valid) in the level above
354  load_hdr_reg : in STD_LOGIC;
355  CRC_out : out STD_LOGIC_VECTOR (8 downto 0);
356  hdr_out_crc9_valid : out STD_Logic
357  );
358 end component;
359 
360 
361 component event_trailer_CRC20 is
362  generic(
363  crc20_G_Poly : std_logic_vector(19 downto 0) := x"8349f"; -- old poly
364  Nbits : positive := 64;
365  CRC_Width : positive := 20;
366  G_Poly: Std_Logic_Vector :=x"c1acf";
367  G_InitVal: std_logic_vector:=x"fffff"
368  );
369  port(
370  CRC : out std_logic_vector(CRC_Width-1 downto 0);
371  Calc : in std_logic;
372  Clock : in std_logic;
373  s_tdata : in std_logic_vector(Nbits-1 downto 0);
374  crc_reset : in std_logic;
375  sel_packet_trailer : in std_logic
376  );
377 end component;
378 
379 component CRC
380  generic(
381  Nbits : positive := 64;
382  CRC_Width : positive := 9;
383 -- G_Poly: Std_Logic_Vector :=x"17d";
384  --G_Poly: Std_Logic_Vector := "101111101";
385  G_Poly: Std_Logic_Vector := "011111011";
386  G_InitVal: std_logic_vector:= "111111111"
387  );
388  port(
389  CRC : out std_logic_vector(CRC_Width-1 downto 0);
390  Calc : in std_logic;
391  Clk : in std_logic;
392  DIn : in std_logic_vector(Nbits-1 downto 0);
393  Reset : in std_logic);
394 end component;
395 
396 component trailer_map
397  generic (
398  jfex : integer := 0
399  );
400  Port (
401  pp_clock : in STD_LOGIC;
402  reset : in STD_LOGIC;
403  current_chan : in STD_LOGIC_VECTOR (4 downto 0);
404  chan_len_error : in STD_LOGIC;
405  chan_hdr_crc_err : in STD_LOGIC;
406  chan_crc20_err : in STD_LOGIC;
407  L1ID_eq : in STD_LOGIC;
408  chan_crc20_samp : in STD_LOGIC;
409  crc9_err_samp : in STD_LOGIC;
410  len_err_samp : in STD_LOGIC;
411  L1ID_eq_samp : in STD_LOGIC;
412  timeout_error : in STD_LOGIC;
413  clear_map : in STD_LOGIC;
414  sel_corr_trailer : in STD_LOGIC;
415  error_map : out STD_LOGIC_VECTOR(11 downto 0);
416  lmem : out STD_LOGIC_VECTOR(3 downto 0);
417  rod_err_map : out STD_LOGIC_VECTOR(6 downto 0);
418  debug_pkt_module_map: out STD_LOGIC_VECTOR(11 downto 0)
419 
420  );
421 end component;
422 
423 component tob_timeout
424  Port ( clock : in STD_LOGIC;
425  reset : in STD_LOGIC;
426  start_timer : in STD_LOGIC;
427  stop_timer : in STD_LOGIC;
428  set_time_1 : in STD_LOGIC_VECTOR(15 downto 0);
429  set_time_n : in STD_LOGIC_VECTOR(15 downto 0);
430  timeout_1 : out STD_LOGIC;
431  timeout_n : out STD_LOGIC;
432  counter_out : out STD_LOGIC_VECTOR(15 downto 0);
433  run_out : out STD_LOGIC
434  );
435 end component;
436 
437 component watchdog is
438  generic ( overflow_clock_count : std_logic_vector(7 downto 0) := x"0f"
439  );
440  Port ( pp_clock : in STD_LOGIC;
441  reset_in : in STD_LOGIC;
442  wdog_disable : in STD_LOGIC;
443  wdog_pet : in STD_LOGIC;
444  wdog_threshold : in STD_LOGIC_VECTOR (15 downto 0);
445  wdog_overflow : out STD_LOGIC
446  );
447 end component;
448 
449 signal s_axis_aresetn : std_logic;
450 --signal m_tvalid : std_logic;
451 --signal m_tlast : std_logic;
452 --signal m_tready : std_logic;
453 --signal header_marker : std_logic;
454 --signal tail_marker : std_logic;
455 --signal m_tdata : STD_LOGIC_VECTOR (95 downto 0);
456 signal tob_data_count : STD_LOGIC_VECTOR (31 downto 0);
457 signal tob_wr_data_count : STD_LOGIC_VECTOR (31 downto 0);
458 signal tob_rd_data_count : STD_LOGIC_VECTOR (31 downto 0);
459 signal hp_empty : std_logic;
460 signal no_other_match : std_logic;
461 signal hdr_reg_valid : std_logic := '0';
462 signal header_reg : STD_LOGIC_VECTOR ((bp_width-1) downto 0);
463 signal header_reg_ex : STD_LOGIC_VECTOR ((header_width-bp_width) downto 0);
464 --signal last_chan : STD_LOGIC_VECTOR (3 downto 0) := "1111";
465 signal empty_out : std_logic := '1';
466 signal poll : std_logic := '0';
467 signal inc_chan : std_logic := '0';
468 signal match_out : std_logic := '0';
469 signal read_active : std_logic := '0';
470 
471 signal load_last_chan : std_logic;
472 signal load_hdr_reg : std_logic;
473 signal fifo_s_tvalid : std_logic;
474 signal fifo_s_tlast : std_logic;
475 
476 signal current_state : state_type;
477 signal next_state : state_type;
478 signal next1 : state_type;
479 signal ctrl_code : controls_type;
480 
481 signal chan_len_cnt : STD_LOGIC_VECTOR (11 downto 0) := "000000000000";
482 signal corrected_length : STD_LOGIC_VECTOR (15 downto 0) := x"0000";
483 signal pkt_len_cnt : STD_LOGIC_VECTOR (15 downto 0) := x"0000";
484 signal pkt_len_cnt_dly : STD_LOGIC_VECTOR (15 downto 0) := x"0000";
485 
486 signal fifo_s_tready : std_logic;
487 signal hdr_fifo_wr : std_logic;
488 signal rod_header : STD_LOGIC_VECTOR (63 downto 0);
489 signal lead_follow_b_reg : std_logic;
490 signal sel_packet_header : std_logic;
491 signal sel_packet_header_2 : std_logic;
492 signal sel_packet_trailer : std_logic;
493 signal chan_len_error : std_logic:= '0';
494 signal dbg_chan_len_error : std_logic:= '0';
495 signal trailer_crc20_calc : std_logic;
496 signal trailer_crc20_reset : std_logic;
497 signal chan_trailer_crc20_calc : std_logic;
498 signal chan_trailer_crc20_reset : std_logic;
499 signal proposed_crc20 : STD_LOGIC_VECTOR (19 downto 0);
500 signal hdr_out_crc9_start : std_logic;
501 signal hdr_out_crc9_valid : std_logic;
502 signal trailer_crc20 : STD_LOGIC_VECTOR (19 downto 0);
503 signal chan_crc20_err : std_logic;
504 signal timeout_error : std_logic;
505 signal dbg_timeout_error : std_logic;
506 signal chan_trailer_crc20 : STD_LOGIC_VECTOR (19 downto 0);
507 signal fifo_s_tdata : STD_LOGIC_VECTOR (bp_width-1 downto 0);
508 signal evnt_sel : STD_LOGIC_VECTOR (3 downto 0);
509 signal next_chan : STD_LOGIC_VECTOR (4 downto 0);
510 signal L1ID_eq : std_logic;
511 signal L1ID_reg_eq : std_logic;
512 signal L1ID_reg_lt : std_logic;
513 signal L1ID_reg_gt : std_logic;
514 signal L1ID_eq_pipe : std_logic;
515 signal BCN : STD_LOGIC_VECTOR (11 downto 0);
516 signal BCID_reg : STD_LOGIC_VECTOR (11 downto 0);
517 --signal BCID_mismatch : STD_LOGIC;
518 signal L1ID : STD_LOGIC_VECTOR (23 downto 0);
519 signal ECRID : STD_LOGIC_VECTOR (7 downto 0);
520 signal orbit : STD_LOGIC_VECTOR (15 downto 0);
521 signal header_reg_0 : STD_LOGIC_VECTOR (31 downto 0);
522 signal header_reg_1 : STD_LOGIC_VECTOR (31 downto 0);
523 signal header_reg_2 : STD_LOGIC_VECTOR (31 downto 0);
524 signal version : STD_LOGIC_VECTOR (2 downto 0);
525 signal pkt_type : STD_LOGIC_VECTOR (3 downto 0);
526 signal header_crc : STD_LOGIC_VECTOR (8 downto 0);
527 signal h_sequence : STD_LOGIC_VECTOR (11 downto 0);
528 signal tob_stream_id : STD_LOGIC_VECTOR (7 downto 0);
529 
530 --signal header_mismatch : std_logic;
531 signal chan_hdr_crc_err : std_logic;
532 signal header_crc_start : std_logic;
533 
534 signal rod_number : STD_LOGIC_VECTOR (1 downto 0);
535 signal rod_link_error_map : STD_LOGIC_VECTOR (11 downto 0);
536 signal rod_error_map : STD_LOGIC_VECTOR (6 downto 0);
537 
538 signal dbg_link_error_map : STD_LOGIC_VECTOR (11 downto 0);
539 signal dbg_error_map : STD_LOGIC_VECTOR (6 downto 0);
540 
541 signal corr_trail_chan : STD_LOGIC_VECTOR (4 downto 0) := "00000";
542 --signal crc20_err_chan : STD_LOGIC_VECTOR (4 downto 0) := "00000";
543 signal LMEM : STD_LOGIC_VECTOR (3 downto 0);
544 signal dbg_LMEM : STD_LOGIC_VECTOR (3 downto 0);
545 
546 signal event_trailer : STD_LOGIC_VECTOR (63 downto 0);
547 signal corr_trailer : STD_LOGIC_VECTOR (63 downto 0);
548 signal L1ID_ttc_hreg : STD_LOGIC_VECTOR (23 downto 0);
549 signal L1id_ttc_32_reg : STD_LOGIC_VECTOR (31 downto 0);
550 signal ECRID_ttc_hreg : STD_LOGIC_VECTOR (7 downto 0);
551 
552 signal S_tdata_swap : STD_LOGIC_VECTOR (63 downto 0);
553 
554 signal m_tdata_i : STD_LOGIC_VECTOR (63 downto 0);
555 signal m_tvalid_i : STD_LOGIC;
556 signal m_tlast_i : STD_LOGIC;
557 signal m_header_marker_i : STD_LOGIC;
558 signal m_tail_marker_i : STD_LOGIC;
559 signal state : state_type;
560 
561 --tob stream signals
562 signal tob_m_tvalid_i : STD_LOGIC;
563 signal tob_m_tlast_i : STD_LOGIC;
564 signal tob_m_tready : STD_LOGIC;
565 signal tob_m_header_marker_i : STD_LOGIC;
566 signal tob_m_tail_marker_i : STD_LOGIC;
567 signal tob_m_tdata_i : STD_LOGIC_VECTOR (63 downto 0);
568 
569 signal s_tlast_del : STD_LOGIC;
570 signal s_tlast_del2 : STD_LOGIC;
571 --signal s_tlast_pulse : STD_LOGIC;
572 --signal chan_crc20_samp : STD_LOGIC;
573 
574 --debug stream signals
575 
576 signal dbg_s_tvalid : STD_LOGIC;
577 signal dbg_s_tlast : STD_LOGIC;
578 signal dbg_s_tready : STD_LOGIC;
579 signal dbg_s_tdata : STD_LOGIC_VECTOR (63 downto 0);
580 signal dbg_header_reg : STD_LOGIC_VECTOR (63 downto 0);
581 signal dbg_header_reg_tmp : STD_LOGIC_VECTOR (63 downto 0);
582 signal dbg_corr_trailer : STD_LOGIC_VECTOR (63 downto 0);
583 signal dbg_stream_id : STD_LOGIC_VECTOR (7 downto 0);
584 --signal dbg_header_crc : STD_LOGIC_VECTOR (8 downto 0);
585 signal dbg_m_tvalid_i : STD_LOGIC;
586 signal dbg_m_tlast_i : STD_LOGIC;
587 signal dbg_m_tready : STD_LOGIC;
588 signal dbg_m_header_marker_i : STD_LOGIC;
589 signal dbg_m_tail_marker_i : STD_LOGIC;
590 signal dbg_m_tdata_i : STD_LOGIC_VECTOR (63 downto 0);
591 
592 signal dbg_crc9_in_flip : STD_LOGIC_VECTOR (63 downto 0);
593 
594 signal dbg_hdr_CRC : STD_LOGIC_VECTOR (8 downto 0);
595 signal dbg_crc9_calc : STD_LOGIC;
596 signal dgb_crc9_reset : STD_LOGIC;
597 signal hdr_in_crc9_reset : STD_LOGIC;
598 signal dbg_sel : STD_LOGIC_VECTOR (1 downto 0);
599 signal sel_dbg_header : STD_LOGIC;
600 signal sel_dbg_trailer : STD_LOGIC;
601 signal sel_corr_trailer : STD_LOGIC;
602 
603 signal dbg_trailer_CRC : STD_LOGIC_VECTOR (19 downto 0);
604 signal dbg_crc20_calc : STD_LOGIC;
605 signal dbg_crc20_in_flip : STD_LOGIC_VECTOR (63 downto 0);
606 signal dgb_crc20_reset : STD_LOGIC;
607 signal dbg_LenCount_Ena : STD_LOGIC;
608 signal dbg_LenCount_Rst : STD_LOGIC;
609 signal dbg_LenCount : STD_LOGIC_VECTOR (14 downto 0);
610 signal dbg_chan_LenCount : STD_LOGIC_VECTOR (11 downto 0);
611 signal dbg_pkt_count_i : STD_LOGIC_VECTOR (31 downto 0);
612 signal tobsel : STD_LOGIC;
613 signal corr_trailer_len_flag : STD_LOGIC;
614 signal corr_trailer_pe_flag : STD_LOGIC;
615 
616 signal chan_crc_dmux_ctrl : STD_LOGIC;
617 signal chan_crc_dmux_data : STD_LOGIC_VECTOR (63 downto 0);
618 signal chan_crc_din : STD_LOGIC_VECTOR (63 downto 0);
619 
620 --output pipe
621 signal m_tdata_buf : STD_LOGIC_VECTOR (63 downto 0);
622 signal m_tvalid_buf : STD_LOGIC;
623 signal m_tlast_buf : STD_LOGIC;
624 signal m_header_marker_buf : STD_LOGIC;
625 signal m_tail_marker_buf : STD_LOGIC;
626 
627 signal tob_pkt_active : STD_LOGIC;
628 
629 signal timeout_1 : STD_LOGIC;
630 signal timeout_n : STD_LOGIC;
631 signal stop_timeout : STD_LOGIC;
632 signal timeout_counter : STD_LOGIC_VECTOR (15 downto 0);
633 signal timeout_run : STD_LOGIC;
634 
635 signal pet_timer : STD_LOGIC;
636 signal clr_build_flag : STD_LOGIC;
637 signal set_build_flag : STD_LOGIC;
638 signal clr_chan_len_cnt : STD_LOGIC;
639 signal inc_corr_counter : STD_LOGIC;
640 signal build_flag : STD_LOGIC;
641 signal last_chan_read : STD_LOGIC;
642 signal any_chan_read : STD_LOGIC;
643 signal chan_enable_del : STD_LOGIC;
644 
645 signal finished_lc : STD_LOGIC;
646 
647 signal reference_lid_0 : STD_LOGIC;
648 
649 signal set_bad_l1id_flag : STD_LOGIC;
650 signal bad_l1id_flag : STD_LOGIC;
651 signal l1id_resync_flag : STD_LOGIC;
652 
653 signal shelf : STD_LOGIC_VECTOR(3 downto 0);
654 signal wdog_pet : STD_LOGIC;
655 signal wdog_overflow_i : STD_LOGIC;
656 
657 signal tempsig : std_logic;--_vector(11 downto 0);
658 
659 signal efex_shelf_num : STD_LOGIC_VECTOR(1 downto 0);
660 signal set_empty_packet_build : std_logic;
661 signal empty_pkt_active : std_logic := '0';
662 
663 
664 signal ttc_rollover_sig : std_logic := '0';
665 signal ttc_rollover_reg : std_logic := '0';
666 
667 
668 signal rx_timer_clear : std_logic := '0';
669 signal l1id_measure_lock : std_logic := '0';
670 signal header_fifo_valid_del : std_logic := '0';
671 signal l1id_measure_reg : STD_LOGIC_VECTOR(31 downto 0) := x"0000_0000"; --l1id of the event being measured
672 signal l1id_measure_time : STD_LOGIC_VECTOR(31 downto 0) := x"0000_0000"; --time being measured for the event
673 signal l1id_measure_last : STD_LOGIC_VECTOR(31 downto 0) := x"0000_0000"; --31-bit copy of time from last event (shift right)
674 signal l1id_measure_max : STD_LOGIC_VECTOR(31 downto 0) := x"0000_0000"; --copy of maximum time from all events
675 signal l1id_max_l1id : STD_LOGIC_VECTOR(31 downto 0) := x"0000_0000"; --l1id of the event with greated wait time
676 signal l1id_measure_last_i : STD_LOGIC_VECTOR(31 downto 0) := x"0000_0000"; --full 32-bit time from last event
677 signal l1id_measure_max_i : STD_LOGIC_VECTOR(31 downto 0) := x"0000_0000"; --copy of maximum time from all events
678 
679 --signal timeout_counter_last_i : STD_LOGIC_VECTOR(15 downto 0) := x"0000";
680 --signal timeout_counter_last_lock : std_logic := '0';
681 signal timeout_1_raw : std_logic := '0';
682 signal timeout_n_raw : std_logic := '0';
683 
684 signal timeout_counter_max_i : STD_LOGIC_VECTOR(15 downto 0) := x"0000";
685 signal max_chan_i : STD_LOGIC_VECTOR(4 downto 0);
686 signal hdr_crc_flag : std_logic := '0';
687 
688 begin
689 
690 -----------------
691 version <= "001";
692 tob_stream_id <= x"01";
693 shelf <= geo_location(4 downto 1);
694 -------------------------
695 
696 --with geo_location(1) select
697 -- efex_shelf_num <= "00" when '0',
698 -- "01" when '1',
699 -- "00" when others;
700 
701 with shelf select
702  efex_shelf_num <= "00" when "0000",
703  "01" when "0001",
704  "00" when others;
705 
706 
707  state_reg : vDFF
708  generic map (StWIDTH)
709  port map (
710  clk => clock,
711  D => next_state,
712  Q => current_state
713  );
714 state <= current_state;
715 state_out <= current_state;
716 
717 event_fifo: event_builder_fifo
718  port map(
719 -- s_axis_tvalid => s_tvalid,
720  s_axis_tvalid => fifo_s_tvalid,
721  s_axis_tready => fifo_s_tready,
722  s_axis_aresetn => s_axis_aresetn,
723  s_axis_aclk => clock,
724  s_axis_tlast => fifo_s_tlast,
725 -- s_axis_tuser(1) => s_header_mark,
726 -- s_axis_tuser(0) => s_trailer_mark,
727  s_axis_tuser(1) => sel_packet_header,
728  s_axis_tuser(0) => sel_packet_trailer,
729 
730 -- s_axis_tdata => s_tdata,
731  s_axis_tdata => fifo_s_tdata,
732 
733  m_axis_tvalid => tob_m_tvalid_i,
734  m_axis_tlast => tob_m_tlast_i,
735  m_axis_tready => tob_m_tready,
736  m_axis_tuser(1) => tob_m_header_marker_i,
737  m_axis_tuser(0) => tob_m_tail_marker_i,
738  m_axis_tdata => tob_m_tdata_i,
739 
740 -- axis_data_count => tob_data_count,
741  axis_wr_data_count => tob_wr_data_count,
742  axis_rd_data_count => tob_rd_data_count
743  );
744 
745 s_axis_aresetn <= not reset;
746 event_fifo_level <= tob_wr_data_count;
747 
748 
749 --ila_event_fifo : event_fifo_ila
750 --PORT MAP (
751 -- clk => clock,
752 -- probe0(0) => fifo_s_tvalid,
753 -- probe1(0) => fifo_s_tlast,
754 -- probe2(0) => fifo_s_tready,
755 -- probe3(0) => s_header_mark,
756 -- probe4(0) => s_trailer_mark,
757 -- probe5(0) => s_axis_aresetn,
758 -- probe6 => fifo_s_tdata,
759 -- probe7(0) => m_tvalid_i,
760 -- probe8(0) => m_tlast_i,
761 -- probe9(0) => m_tready,
762 -- probe10(0) => m_header_marker_i,
763 -- probe11(0) => m_tail_marker_i,
764 -- probe12 => m_tdata_i,
765 -- probe13 => state
766 --);
767 
768 -----------------------------
769 ----output pipe--------------
770 -----------------------------
771 process (clock) begin
772  if rising_edge (clock) then
773  m_tdata_buf <= m_tdata_i;
774  m_tvalid_buf <= m_tvalid_i;
775  m_tlast_buf <= m_tlast_i;
776  m_header_marker_buf <= m_header_marker_i;
777  m_tail_marker_buf <= m_tail_marker_i;
778  end if;
779 end process;
780 
781 m_tdata <= m_tdata_buf;
782 m_tvalid <= m_tvalid_buf;
783 m_tlast <= m_tlast_buf;
784 m_header_marker <= m_header_marker_buf;
785 m_tail_marker <= m_tail_marker_buf;
786 
787 
788 --m_tdata <= m_tdata_i;
789 --m_tvalid <= m_tvalid_i;
790 --m_tlast <= m_tlast_i;
791 --m_header_marker <= m_header_marker_i;
792 --m_tail_marker <= m_tail_marker_i;
793 
794 ---------------------------------------------------
795 
796 
797 
798 
799 
800 
801 
802 --hp_empty is true if no higher priority queue is empty
803 hp_empty <= not (empty_0 or empty_1 or empty_2 or empty_3);
804 
805 --check that no other queue is matched to this header
806 no_other_match <= not (match_0 or match_1 or match_2 or match_3);
807 
808 
815  process (clock,
816  reset,
817  current_state,
818  flx_backpressure,
819  flx_bp_enable,
820  header_fifo_valid,
821  chan_enable,
822  current_chan,
823  num_chan,
824  any_chan_read,
825  timeout_1,
826  timeout_n,
827  s_tvalid,
828  tob_pkt_active,
829  lead_follow_b_reg,
830  chan_in,
831  s_header_mark,
832  s_hdr_crc_tag,
833  comb_error,
834  L1ID_reg_eq,
835  TTC_ignore,
836  L1ID_eq,
837  empty_pkt_active,
838  s_trailer_mark,
839  next_chan,
840  chan_enable_del,
841  chan_crc20_err,
842  chan_len_error,
843  last_chan_read,
844  bad_l1id_flag,
845  first_chan
846  )
847  begin
848  case current_state is
855  when wait_for_event =>
856  if (((flx_backpressure and flx_bp_enable) = '1') or (stop_proc = '1')) then
857  next1 <= wait_for_event;
858  elsif header_fifo_valid = '1' then
859  next1 <= read_ttc;
860  else
861  next1 <= wait_for_event;
862  end if;
863  ctrl_code <= wait_for_event_o;
864 
871  when read_ttc =>
872  next1 <= idle_state;
873  ctrl_code <= read_ttc_o;
874 
875 
884  when chan_timeout =>
885  next1 <= check_enable;
886  ctrl_code <= chan_timeout_o;
887 
888 
900  when check_enable => -- pet_timer
901  if (chan_enable = '0') and (current_chan = num_chan) and (any_chan_read = '1') then
902  next1 <= trailer_build_2;
903 
904  elsif (chan_enable = '0') and (current_chan /= num_chan) then
905  next1 <= chan_timeout;
906  else
907  next1 <= idle_state; --ef 2021_07_02 potential lockup, so adding pet_timer to check_enable
908  end if;
909  ctrl_code <= check_enable_o;
910 
911 
918  when discard_event =>
919  next1 <= wait_for_event;
920  ctrl_code <= discard_event_o;
921 
922 
934 
935 
936 
937 --> Idle State is entered on reset or at the end of building an event packet
938 --> Exit to normal packet build (load_header) when an L1A has been received and data packet has arrived on the first channel. (this will be updated to include a timeout feature if a packet has not arrived after the L1A)
939 --> Exit to a debug packet build (dbg_header_build) if the received TOB packet has a header CRC error. (update to include further errors as comb_error) (comb_error is currently tied to '0')
940 --> The initial terms in the equations apply to the multi-processor configuration (((lead_follow_b_reg ='1') or (current_chan < chan_in) or ((current_chan = num_chan) and (chan_in >= first_chan)and chan_in /= num_chan))
941 --> Lead_follow_b ='1' indicates that this processor processor is the Lead processor or ONLY processor. Lead_follow_b_reg = '0' indicates that this processor should follow the one ahead of it in the daisy chain of processors
942 --> in terms of what channels it works on. It needs to stay behind so that each processor is working on its own event.
943 --> Chan_in indicates the channel that the next higher priority processor is currently working on.
944 -->
945  --State-00 ----
946  when idle_state => --hdr_out_crc9_start, Debug header CRC calc, Debug header CRC reset
947 
948 
949 -- if ((lead_follow_b_reg ='1') or (current_chan < chan_in) or ((current_chan=num_chan) and (chan_in >= "0000") and (chan_in /= num_chan)) and (s_tvalid = '1') and (s_header_mark = '1') and (comb_error = '0')) then next1 <=load_header;
950 
951 
952 -- if ((lead_follow_b_reg ='1') or (current_chan < chan_in) or ((current_chan = num_chan) and (chan_in >= first_chan)and chan_in /= num_chan))
953 -- and (s_tvalid = '1') and (s_header_mark = '1') and (s_hdr_crc_tag = '0') and (comb_error = '0') and ((header_fifo_valid = '1') or (TTC_ignore = '1'))
954 -- then next1 <= load_header;
955 --
956 -- elsif ((lead_follow_b_reg ='1') or (current_chan < chan_in) or ((current_chan = num_chan) and (chan_in >= first_chan)and chan_in /= num_chan))
957 -- and (s_tvalid = '1') and (s_header_mark = '1') and (s_hdr_crc_tag = '1') and (comb_error = '0') and ((header_fifo_valid = '1') or (TTC_ignore = '1'))
958 -- then next1 <= dbg_header_build;
959 --
960 -- else next1 <= idle_state;
961 -- end if;
962 
963  -- the decision below was supposed to check for multiprocessor mode timeout, but does not currently work because
964  -- current_chan is always >= chan_in. It needs to have lead_follow and other multiprocessor checking
965 
966  -- if ((current_chan >= chan_in) and (timeout_1 = '1')) --timed out waiting for a higher priority processor
967  -- then next1 <= wait_for_event; --reset the timer and try again
968 
969 
970 -- State-00----idle_state
977 
978  if (timeout_1 = '1') and (current_chan = first_chan) then
979  if (current_chan = num_chan) then --single channel case
980  next1 <= start_empty_pkt;
981  else
982  next1 <= chan_timeout;
983  end if;
984 
985  elsif (timeout_n = '1') and ((s_tvalid = '0')) and (current_chan > first_chan) then
986 
987  if (current_chan = num_chan) and (tob_pkt_active = '0') then
988 -- next1 <= discard_event; --no TOBs have arrived for this event and so there must have been an L1A error
989 -- next1 <= wait_for_event; --no TOBs have arrived for this event and so there must have been an L1A error or tobs are tured off
990  --changed from discard_event because the event should have been already read anyway
991  next1 <= start_empty_pkt; --no TOBs have arrived for this event and so an empty packet should be sent.
992 
993  else next1 <= chan_timeout; --no tobs arrived for this channel, time to increment channel and try again
994  end if;
995  --this is the begining of normal packet building
996  elsif ((lead_follow_b_reg ='1') or (current_chan < chan_in) or ((current_chan = num_chan) and (chan_in >= first_chan)and chan_in /= num_chan))
997  and (s_tvalid = '1') and (s_header_mark = '1') and (s_hdr_crc_tag = '0') and (comb_error = '0') then --and ((header_fifo_valid = '1') or (TTC_ignore = '1')) then
998  --if (L1ID_ttc_hreg = s_tdata(55 downto 32)) or (ttc_ignore = '1') then
999  if (L1ID_reg_eq = '1') then
1000  next1 <= start_reading;
1001 
1002 -- elsif ((l1id_reg_eq = '0') or (s_hdr_crc_tag = '1')) then --there is an inappropriate packet in the queue due to incorrect L1ID or crc9 error
1003 -- next1 <= dbg_bad_l1ID;
1004 
1005  elsif (L1ID_reg_lt = '1') then --this is a packet from a previous event
1006  next1 <= dbg_bad_l1ID;
1007 
1008  elsif (L1ID_reg_gt = '1') then --this is a packet from an event which is more recent than the one being processed
1009  --"L1iD greater Than" is limited to meaning Greater Than but not by more than 16. If the L1ID mismatch is > 16, then something else is wrong and the packet can no longer be left in place.
1010  --note that the L1ID_reg_gt test has to follow the L1ID_reg_eq and L1ID_reg_lt tests because it is not strictly greater, it is (<= L1ID_ttc_32_reg + 16)
1011  next1 <= chan_timeout; --finish_reading; --leave this packet in place
1012 
1013  else
1014  next1 <= dbg_header_build; --start building a debug packet
1015  end if;
1016 
1017 
1018 --if the packet header has a crc9 error, build a debug packet
1019  elsif ((lead_follow_b_reg ='1') or (current_chan < chan_in) or ((current_chan = num_chan) and (chan_in >= first_chan)and chan_in /= num_chan))
1020  and (s_tvalid = '1') and (s_header_mark = '1') and (s_hdr_crc_tag = '1') and (comb_error = '0') --and ((header_fifo_valid = '1') or (TTC_ignore = '1'))
1021  then next1 <= dbg_header_build;
1022 
1023  else
1024  next1 <= idle_state; --wait for a tob packet to arrive or timeout
1025 
1026  end if;
1027 
1028 
1029 
1030 
1031 
1032 
1033  ctrl_code <= idle_o;
1034 
1035 
1042 -- state 01 ----load_header
1043 
1044 
1045 -->load_header is the first state of normal packet building.
1046 -->(load_hdr_reg/clr pkt length <= '1'), (load_last_chan_pointer<= '1')
1047 --> Exit to start_reading if the TTC L1ID and the packet L1ID match
1048 --> If the L1IDs do not match, then take action based bpon wheth the packet L1ID < or > TTC L1ID
1049 --> if packet L1ID < TTC L1ID, then it is old and should be delt with as a debugug packet
1050 --> if packet L1ID > TTC L1ID, then the packet is ahead of the TTC processing. It should be skipped and picket up in next build
1051 --> (or maybe, if it is too far advanced, it is probably an error. Although this should be picked up in the crc)
1052 
1053 --begin processing first_channel and packet header
1054 
1055  when load_header => --load last_chan_pointer, load_hdr_reg/clr pkt length
1056 
1057 -- if (L1ID_ttc_hreg = s_tdata(55 downto 32) or (TTC_ignore = '1')) and (s_header_mark = '1') and (comb_error = '0') then
1058 -- if (L1ID = s_tdata(55 downto 32) or (TTC_ignore = '1')) and (s_header_mark = '1') and (comb_error = '0') then
1059  if ((L1ID_eq = '1') or (TTC_ignore = '1')) and (s_tvalid = '1') and (s_header_mark = '1') and (comb_error = '0') then
1060  next1 <= start_reading;
1061  -- elsif (L1ID_ttc_hreg /= s_tdata(55 downto 32) AND (TTC_ignore = '0')) and (s_header_mark = '1') and (comb_error = '0') then
1062 -- elsif (L1ID /= s_tdata(55 downto 32) AND (TTC_ignore = '0')) and (s_header_mark = '1') and (comb_error = '0') then
1063  elsif ((L1ID_eq = '0') AND (TTC_ignore = '0')) and (s_tvalid = '1') and (s_header_mark = '1') and (comb_error = '0') then
1064 -- next1 <= idle_state; --going to idle is a temp patch. If the header doesn't match the ttc, then action is needed: start a debug packet?
1065  next1 <= dbg_bad_l1ID; --ef 2021_07_02 dbg_bad_l1ID
1066 
1067 --ef experimental --what to do if there is no tvalid at this stage
1068 -- elsif ((s_tvalid = '0') and ((timeout_1 = '0' and current_chan = first_chan) or (timeout_n = '0' and current_chan /= first_chan)) then
1069 -- next1 <= load_header;
1070 
1071 
1072  else
1073  --next1 <= idle_state; --this is a potential lock-up that needs to be fixed because timeout isn't running
1074  next1 <= chan_timeout; --ef 2021_07_02 it shouldn't get to this state if there is no legal packet, but if so, better treated as a channel timeout
1075  end if;
1076  ctrl_code <= load_header_o;
1077 
1078 
1079 
1089 
1090  when start_reading =>
1091  next1 <= header_build;
1092  ctrl_code <= start_reading_o;
1093 
1094 
1098 --> this is that state when the first header word is placed into the event fifo
1099 --> FIFO s_tvalid, hdr_reg_valid, sel_pkt_header_1, event_trailer_crc20_reset, chan_trailer_crc_reset <='1'
1100 --> exit always to state "header_build_2"
1101 
1102  when header_build => --chan_trailer_crc_reset, event_trailer_crc20_reset, sel_packet_header_1, hdr_reg_valid, FIFO s_tvalid
1103  next1 <= header_build_2;
1104  ctrl_code <= header_build_o;
1105 
1111  -- perhaps this should now be chan_timeout, but chan_emable should be '1' since this is the first channel.
1112  --functionality of this state could be extended to producing the
1113 
1114 --> exit to state "continue_reading" under normal conditions
1115  when header_build_2 =>
1116  -- if (chan_enable = '0') then
1117 
1118  -- -ef 21jul-21 next1 <= finish_reading;
1119  -- next1 <= check_enable; --new
1120 
1121  -- else
1122  --2022_02_15 added for empty pkt generation
1123  if (empty_pkt_active = '1') then
1124  next1 <= trailer_build_2;
1125  else
1126 
1127  next1 <= continue_reading;
1128  end if;
1129  ctrl_code <= header_build_2_o;
1130 
1139 -- ********these terms appear to be redundant: event_trailer_crc20_calc, chan_trailer_crc_calc*******
1140 
1141  when continue_reading =>
1142  -- if (s_tvalid = '1') and (s_trailer_mark = '1') and (current_chan = num_chan) and (chan_crc20_err = '1') then --or aurora errors must be added
1143  -- next1 <= pr_corr_trailer;
1144 
1145  if (s_tvalid = '1') and (s_trailer_mark = '1') and (current_chan = num_chan) --and (chan_crc20_err = '0') then
1146  then next1 <= trailer_build;
1147 
1148 
1149  elsif (s_tvalid = '1') and (s_trailer_mark = '1') and (current_chan /= num_chan) then
1150  next1 <= finish_reading;
1151  else
1152  next1 <= continue_reading;
1153  end if;
1154  ctrl_code <= continue_reading_o;
1155 
1165 
1166 --> (hdr_reg_valid, increment chan <= '1')
1167 -->
1168  when finish_reading =>
1169  if (next_chan >= chan_in) and (lead_follow_b_reg = '0') then
1170  next1 <= wait_chan_in;
1171  -- else next1 <= continue_polling;
1172 -- else next1 <= check_error;
1173  else next1 <= wait_for_hdr;
1174  end if;
1175  ctrl_code <= finish_reading_o;
1176 
1177 
1187  when wait_for_hdr =>
1188 
1189  if (chan_enable = '0' and chan_enable_del = '0') then --the current channel is disabled. The delay is because the channel pointer has already been incremented
1190  next1 <= finish_reading;
1191  elsif (chan_enable_del = '1')and (timeout_n = '0') and (timeout_1 = '0') and ((chan_crc20_err = '1') or (chan_len_error = '1')) then --or aurora error flag (set during continue reading)
1192  next1 <= pr_corr_trailer;
1193  else
1194  next1 <= check_error;
1195  end if;
1196  ctrl_code <= wait_for_hdr_o;
1197 
1198 
1207 
1211 
1212  when check_error =>
1213 
1214 --stall for other processor
1215  if (chan_in = current_chan) and (timeout_n = '1')
1216  then next1 <= wait_for_hdr; --restart timer and wait for higher priority processor
1217 
1218 --timeout last channel
1219  elsif (timeout_n = '1') and (s_tvalid = '0') and (current_chan = num_chan) then
1220  if (tob_pkt_active = '1') then --if a packet has been started, then add a trailer and finish
1221  next1 <= trailer_build;
1222 
1223  else --if no packet started, then discard or send the empty packet
1224  next1 <= discard_event;
1225  end if;
1226 
1227 
1228 --timeout other channels
1229  elsif (timeout_n = '1') and ((s_tvalid = '0')) --tvalid is instead of s_header_mark is used in case of alignment error
1230  then next1 <= finish_reading; --increment channel, perhaps chan_timeout
1231 
1232 
1233 
1234 --crc9 error
1235  elsif ((s_tvalid = '1') and (s_header_mark = '1') and (comb_error = '0') and (chan_enable = '1') and (s_hdr_crc_tag = '1')) then
1236  next1 <= dbg_header_build;
1237 
1238 
1239 
1240 
1241 -- new and untested
1242 
1243 
1244 -----future TOB encountered, leave it in place ------------------------------
1245  --this code almost works, but the strategy of leaving future tops in place may be flawed. It is therefore commented out for now
1246  elsif ((s_header_mark = '1') and (comb_error = '0') and (chan_enable = '1') and (L1ID_reg_eq = '0')) and (L1ID_ttc_32_reg < s_tdata (63 downto 32)) and (l1id_resync_enable = '1') then
1247  if (current_chan = num_chan) and (tob_pkt_active = '1') then --if a packet has been started, then add a trailer and finish
1248  next1 <= trailer_build;
1249  else
1250  next1 <= finish_reading;
1251  end if;
1252 --2023_12_06 new future tob
1253 elsif (L1ID_reg_gt = '1') then --this is a packet from an event which is more recent than the one being processed
1254  --"L1iD greater Than" is limited to meaning Greater Than but not by more than 16. If the L1ID mismatch is > 16, then something else is wrong and the packet can no longer be left in place.
1255  --note that the L1ID_reg_gt test has to follow the L1ID_reg_eq and L1ID_reg_lt tests because it is not strictly greater, it is (<= L1ID_ttc_32_reg + 16)
1256  next1 <= finish_reading; --chan_timeout; --finish_read
1257 ----end of future tob processing---------------------
1258 ---------
1259 --L1ID or crc9 error
1260  elsif ((s_tvalid = '1') and (s_header_mark = '1') and (comb_error = '0') and (chan_enable = '1') and ((L1ID_reg_eq = '0') or (s_hdr_crc_tag = '1'))) then
1261  ---send debug packets as long as the packet_l1ID is older than the event. THIS DOES NOT TAKE L1ID WRAP AROUND INTO ACCOUNT
1262  -- elsif ((s_header_mark = '1') and (comb_error = '0') and (chan_enable = '1') and ((s_tdata(55 downto 32) < L1ID_ttc_hreg ) or (ttc_ignore = '1'))) then
1263  next1 <= dbg_bad_l1ID;
1264 
1265 
1266 --normal condition: header is correct, so poll the channel*****
1267  elsif ((s_tvalid = '1') and (s_header_mark = '1') and (comb_error = '0') and (chan_enable = '1') and (s_hdr_crc_tag = '0') and (L1ID_reg_eq = '1')) then
1268  next1 <= poll_early;
1269 
1270 --channel not enabled (middle chan)
1271  elsif (chan_enable = '0') and (current_chan /= num_chan) then
1272  next1 <= finish_reading;
1273 
1274 --channel not enabled (last chan)
1275  elsif (chan_enable = '0') and (current_chan = num_chan) then
1276  next1 <= trailer_build;
1277 
1278  else
1279  next1 <= check_error; --wait until header mark is valid and no errors are present or timeout
1280  --note that the processor has been seen to be stuck in this state, but the conditions have yet to be determined/fixed
1281 
1282 -- next1 <= finish_reading; --if channel is enabled, but there is no header mark, then possibly finish reading
1283  --this branch has not been properly thought through or verified......
1284  --it ws changed from branching to itself after seeing it stuck in this condition one time
1285  --there may be more branches needed based upon other conditions
1286 
1287  end if;
1288  -- if ((s_header_mark = '1') and (comb_error = '0') and (chan_enable = '1') and (s_hdr_crc_tag = '1')) then
1289  -- next1 <= dbg_header_build;
1290  --
1291  -- elsif ((s_header_mark = '1') and (comb_error = '0') and (chan_enable = '1') and (s_hdr_crc_tag = '0')) then
1292  -- --need to check L1ID here before polling - if mismatch, then
1293  -- --if TTC L1ID > header L1ID, then send to debug
1294  -- --elsif TTC L1ID < header L1ID skip this channel by going to finish_reading
1295 ---- next1 <= continue_polling;
1296 -- next1 <= poll_early;
1297 --
1298 -- elsif (chan_enable = '0') and (current_chan /= num_chan) then
1299 -- next1 <= finish_reading;
1300 --
1301 -- elsif (chan_enable = '0') and (current_chan = num_chan) then
1302 -- next1 <= trailer_build;
1303 --
1304 -- else
1305 -- next1 <= check_error; --temporary: wait until header mark is valid and no errors are present
1306 --
1307 -- end if;
1308 
1309 
1310 
1311  ctrl_code <= check_error_o;
1312 
1319 
1320  when poll_early =>
1321  next1 <= continue_polling;
1322  ctrl_code <= poll_early_o;
1323 
1334 
1335  when continue_polling =>
1336 
1337 --normal case: packet header matches the TTC header register
1338  if ((l1ID_reg_eq = '1') or (TTC_ignore = '1')) and (s_tvalid = '1') and (s_header_mark = '1') and (comb_error = '0') and (chan_enable = '1') and (s_hdr_crc_tag = '0') then --check that the next channel matches the header register
1339 
1340  next1 <= header_blocking;
1341 
1342 --
1343 --crc error test
1344 
1345  -- elsif ((s_header_mark = '1') and (comb_error = '0') and (chan_enable = '1') and (s_hdr_crc_tag = '1')) then
1346  -- next1 <= dbg_header_build;
1347 
1348 
1349 
1350 
1351  elsif (chan_enable = '0') then
1352  if (current_chan = num_chan) then
1353  next1 <= trailer_build;
1354  else
1355  next1 <= finish_reading;
1356  end if;
1357  else
1358  next1 <= check_error;
1359  --next1 <= continue_polling; --this looks wrong: but, I don't think you should ever get here
1360  -- l1ID mismatch and crc error are checked in check_error. why poll again?
1361  --answer: if no packet has actually arrived after polling, then stay here until timeout
1362  -- add timeout check here -- (amount of time spent in continue_polling)
1363  end if;
1364  ctrl_code <= continue_polling_o;
1365 
1370  when header_blocking =>
1371 
1372  next1 <= continue_reading;
1373  ctrl_code <= header_blocking_o;
1374 
1375 
1380  when trailer_build =>
1381  next1 <= eval_chan_crc20;
1382  ctrl_code <= trailer_build_o;
1383 
1384 
1391 
1392  when eval_chan_crc20 =>
1393 
1394 --this is new 2021_12_07
1395 -- if the last channel times out, then build the trailer, not the corrective trailer? or perhaps do corr trailer and then real trailer if last chan?
1396  if ((timeout_n = '1') and (current_chan = num_chan) and (tob_pkt_active = '1')) then
1397  next1 <= trailer_build_2;
1398  ----
1399 
1400  elsif ((chan_crc20_err = '1') or (chan_len_error = '1')) then --or timeout?
1401  next1 <= pr_corr_trlr_lc;
1402  else
1403  next1 <= trailer_build_2;
1404  end if;
1405  ctrl_code <= eval_chan_crc20_o;
1406 
1407 
1408 
1413 
1414  when trailer_build_2 =>
1415 -- if (chan_crc20_err = '1') then
1416  -- next1 <= trlr_bld_2_lc;
1417  -- else
1418  next1 <= trailer_build_3;
1419  -- end if;
1420  ctrl_code <= trailer_build_2_o;
1421 
1422 
1430 
1431  when trailer_build_3 => --sel_packet_trailer, hdr_reg_valid
1432  next1 <= trailer_mux;
1433  ctrl_code <= trailer_build_3_o;
1434 
1435 
1440 
1441  when trailer_mux =>
1442  next1 <= wait_for_event;
1443  ctrl_code <= trailer_mux_o;
1444 
1445 
1446 --in the cas
1447 -- when trailer_mux_2 =>
1448 -- next1 <= idle_state;
1449 -- ctrl_code <= trailer_mux_2_o;
1450 
1451 
1455 
1456  when wait_chan_in =>
1457  if (next_chan >= chan_in) then next1 <= wait_chan_in;
1458  else next1 <= continue_polling;
1459  end if;
1460  ctrl_code <= wait_chan_in_o;
1461 
1462 
1465  when pr_corr_trailer =>
1466  next1 <= wait_corr_crc;
1467  ctrl_code <= pr_corr_trailer_o;
1468 
1471  when wait_corr_crc =>
1472  next1 <= add_corr_trailer;
1473  ctrl_code <= wait_corr_crc_o;
1474 
1477  when add_corr_trailer =>
1478  if (current_chan = num_chan) and (last_chan_read = '1') then
1479  next1 <= trailer_build_3; --or maybe trailer_build 2 or 3
1480  else
1481  next1 <= check_error;
1482  end if;
1483  ctrl_code <= add_corr_trailer_o;
1484 
1485  -->corrective trailer processing for the last channel
1486  --> the last channel requires a special sequence that
1487  --> 1) allows the original crc20 to be calculated
1488  --> 2) then allows the corrective trailer crc20 to be calculated and added to the fifo
1489  --> 3) then finally calculates the event crc20 having added in the corrective trailer
1490 
1491  -- when trlr_bld_2_lc =>
1492  -- if (chan_crc20_err = '1') then
1493  -- next1 <= pr_corr_trlr_lc;
1494  -- else
1495  -- next1 <= trailer_build_3;
1496  -- end if;
1497 -- ctrl_code <= trlr_bld_2_lc_o;
1498 
1501  when pr_corr_trlr_lc =>
1502  next1 <= wait_corr_crc_lc;
1503  ctrl_code <= pr_corr_trlr_lc_o;
1504 
1507  when wait_corr_crc_lc =>
1508  next1 <= add_corr_trlr_lc;
1509  ctrl_code <= wait_corr_crc_lc_o;
1510 
1513  when add_corr_trlr_lc =>
1514  if (current_chan = num_chan) and (last_chan_read = '1') then
1515  next1 <= trailer_build_2;
1516  else
1517  next1 <= check_error; --is this path needed? why not always go to trailer_build_2 from this state?
1518  end if;
1519  ctrl_code <= add_corr_trlr_lc_o;
1520 
1521 
1523 
1524 
1528 
1529 
1530  when dbg_header_build =>
1531  next1 <= dbg_header_load;
1532  ctrl_code <= dbg_header_build_o;
1533 
1536  when dbg_header_load =>
1537  -- next1 <= dbg_packet_load;
1538  next1 <= dbg_pkt_load_1st;
1539  ctrl_code <= dbg_header_load_o;
1540 
1542 -- state 28 ---- Debug Packet Load (first cyc)
1545  when dbg_pkt_load_1st =>
1546  if (s_tvalid = '1') and (s_trailer_mark = '1') then
1547  next1 <= dbg_trailer_build;
1548  else
1549  next1 <= dbg_packet_load;
1550  end if;
1551  ctrl_code <= dbg_pkt_load_1st_o;
1552 
1554 -- state 22 ---- Debug Packet Load
1555  when dbg_packet_load =>
1556  if (s_tvalid = '1') and (s_trailer_mark = '1') then
1557  next1 <= dbg_trailer_build;
1558  else
1559  next1 <= dbg_packet_load;
1560  end if;
1561  ctrl_code <= dbg_packet_load_o;
1562 
1565  when dbg_trailer_build =>
1566  next1 <= dbg_trail_build_2;
1567  ctrl_code <= dbg_trailer_build_o;
1568 
1571  when dbg_trail_build_2 =>
1572  next1 <= dbg_trail_build_3;
1573  ctrl_code <= dbg_trail_build_2_o;
1574 
1575 -- state 25 ----
1576  -- when dbg_trail_build_3 =>
1577  -- next1 <= dbg_trailer_load;
1578  -- ctrl_code <= dbg_trail_build_3_o;
1579 
1580 -- state 25 ----
1581 -- when dbg_trail_build_3 => -- sel_dbg_trailer
1582 -- if (current_chan < num_chan) and (bad_l1id_flag = '1') and (s_header_mark = '0') then --there is not another packet, so move to the next channel
1583 -- next1 <= dbg_trailer_load; --increments channel because all of the packets in this channel fifo have been read out
1584 --
1585 -- elsif (((current_chan = num_chan) and (tob_pkt_active = '1')) or (bad_l1id_flag = '1')) then
1586 -- next1 <= dbg_trlr_ld_last; --does not increment channel because that will happen after the tob trailer is added
1587 -- else
1588 -- next1 <= dbg_trailer_load; --increments channel
1589 -- end if;
1590 -- ctrl_code <= dbg_trail_build_3_o;
1591 
1594  when dbg_trail_build_3 =>
1595 
1596  if (current_chan = first_chan) and (bad_l1id_flag = '1') and (s_tvalid = '0' and s_header_mark = '0' and timeout_1 = '1') then
1597 
1598  next1 <= dbg_trlr_inc_chan; --first channel has timed out and there is no tob packet waiting behind
1599  -- next1 <= dbg_trlr_ld_last; --this option would cause it to wait for the next packet to arrive
1600 
1601  --experiment 2023_11_29
1602  elsif (current_chan = first_chan) and timeout_1 = '0' then
1603  next1 <= dbg_trlr_ld_last;
1604 
1605  elsif (current_chan = num_chan) and (bad_l1id_flag = '1') and (s_tvalid = '0' and s_header_mark = '0') then
1606  next1 <= dbg_trlr_ld_last;
1607 
1608  --2024_11_27 specific action for header crc error on middle channel
1609  elsif (current_chan /= num_chan) and (current_chan /= first_chan)and (hdr_crc_flag = '1') then
1610  next1 <= dbg_trlr_inc_chan;
1611 
1612 
1613  --2023_12_06 removing below condition
1614  -- elsif (current_chan /= first_chan) and (bad_l1id_flag = '1') and (s_tvalid = '0' and s_header_mark = '0') then -- and timeout_n = '1') then --there is not another packet, so move to the next channel
1615  -- next1 <= dbg_trlr_inc_chan;
1616 
1617 
1618  ----not tested ---
1619 -- elsif ((bad_l1id_flag = '1') and (s_tvalid = '1' and s_header_mark = '1' and (L1ID_ttc_32_reg < s_tdata (63 downto 32)))) then
1620  ---- next1 <= dbg_trailer_load; --the next packet in the fifo is from a newer event so move to the next channel
1621  -- next1 <= dbg_trlr_inc_chan;
1622  -------
1623 --CAUTION!!
1624 --If a channel receives a packet with a bad l1id, it must first ship the packet as debug.
1625 --Then it can look at the packet behind it, but ONLY if that packet has already arrived.
1626 --It CAN NOT initiate a timeout sequence and wait for a new packet, because that process could go on forever.
1627 -- It could end up waiting until a packet from a new event arrives which will be a l1id mismatch and it will ship that as debug
1628 -- it may end up stuck in that loop forever.
1629 --This is why the code below is looking for tvalid and header mark to be already active rather than waiting
1630 
1631 
1632 --2023_12_06 removing tvalid and header mark requirements from below
1633  elsif (current_chan < num_chan) and (bad_l1id_flag = '1') then --and (s_tvalid = '1' and s_header_mark = '1') then
1634  next1 <= dbg_trlr_ld_last; --does not increment channel because there is another packet in the input fifo
1635 
1636  elsif (((current_chan = num_chan) and (tob_pkt_active = '1')) or (bad_l1id_flag = '1' and s_tvalid = '1' and s_header_mark = '1' and timeout_n = '0') ) then
1637  next1 <= dbg_trlr_ld_last; --does not increment channel because that will happen after the tob trailer is added
1638 
1639  elsif(current_chan = num_chan) and (tob_pkt_active = '0') and (bad_l1id_flag = '1') then --all channels have had l1id mismatch or crc9
1640  next1 <= dbg_trlr_ld_last;
1641  --temporarily removing this statement 2021_12_10
1642  -- elsif (current_chan = first_chan and timeout_1 = '0') or (current_chan /= first_chan and timeout_n = '0') then
1643  -- next1 <= dbg_trail_build_3; --stay here until timeout in case the correct tob packet arrives
1644  else
1645  -- next1 <= dbg_trailer_load; --increments channel
1646  next1 <= dbg_trlr_inc_chan;
1647 
1648  end if;
1649  ctrl_code <= dbg_trail_build_3_o;
1650 
1653  when dbg_trlr_inc_chan =>
1654  next1 <= dbg_trailer_load;
1655  ctrl_code <= dbg_trlr_inc_chan_o;
1656 
1659  when dbg_trailer_load =>
1660  -- if (current_chan = first_chan) then
1661  if (tob_pkt_active = '0') then -- no event header has been built, so go back to idle
1662  next1 <= idle_state;
1663  -- elsif (current_chan < num_chan) then
1664  elsif (current_chan /= first_chan) then
1665  next1 <= check_error;
1666  -- elsif (current_chan = num_chan) and (tob_pkt_active = '1') then --it needs to complete the TOB packet which won't have finished
1667  -- next1 <= trailer_build_2;
1668 
1669 
1670 
1671  --not that if trailer_build_2, trailer_build_3, and trailer_mux change, then new,
1672  -- equivalent dbg states should be added below to replace them .
1673  -- Otherwise a dbg packet on the last channel will cause problems
1674 
1675  else
1676  next1 <= wait_for_event; --I don't believe it should get here.
1677  end if;
1678 
1679  ctrl_code <= dbg_trailer_load_o;
1680 
1683  when dbg_trlr_ld_last =>
1684  -- next1 <= continue_polling;
1685  if (current_chan = first_chan) then --need to go back and create the header and evaluate timeout
1686  next1 <= idle_state; --this is a lock-up when there is no TOB packet available in this channel?
1687  elsif (current_chan < num_chan) then
1688  next1 <= dbg_wait_for_hdr; --check_error; --ef 2023_11_29
1689 --ef 2022_01_25 ch3_crc9_sim bad_l1id flag is set in this state and prevents finishing the packet properly
1690 --so, removing (bad_l1id_flag = '0' requirement. this makes the following statement useless, but I have not yet commented it out
1691  elsif (current_chan = num_chan) and (tob_pkt_active = '1') and (bad_l1id_flag = '0') then --it needs to complete the TOB packet which won't have finished
1692  next1 <= trailer_build_2;
1693 
1694 --ef 2022_12_15 added stvalid to below line and added line after that
1695 -- elsif (current_chan = num_chan) and (tob_pkt_active = '1') and (bad_l1id_flag = '1') then --it needs to complete the TOB packet which won't have finished
1696 -- next1 <= check_error;
1697 
1698  elsif (current_chan = num_chan) and (tob_pkt_active = '1') and (bad_l1id_flag = '1') and (s_tvalid = '1') then --it needs to complete the TOB packet which won't have finished
1699  next1 <= check_error;
1700 
1701  elsif (current_chan = num_chan) and (tob_pkt_active = '1') and (bad_l1id_flag = '1') and (s_tvalid = '0') then --it needs to complete the TOB packet which won't have finished
1702  next1 <= trailer_build_2;
1703 
1704  --ef 2022-12-16 adding l1id_resync_flag - two consecutive events with no channels matching sends back to idle to wait for the next packet
1705  elsif (current_chan = num_chan) and (tob_pkt_active = '0') and (bad_l1id_flag = '1') and (l1id_resync_flag = '1') then --it is finished since no tob packet was started - all channels had l1id mismatch or crc9
1706 -- next1 <= idle_state;
1707  next1 <= attempt_resync;
1708 
1709  elsif (current_chan = num_chan) and (tob_pkt_active = '0') and (bad_l1id_flag = '1') and (l1id_resync_flag = '0') then --it is finished since no tob packet was started - all channels had l1id mismatch or crc9
1710  next1 <= wait_for_event;
1711 
1712  --note that if trailer_build_2, trailer_build_3, and trailer_mux change, then new,
1713  -- equivalent dbg states should be added below to replace them .
1714  -- Otherwise a dbg packet on the last channel will cause problems
1715 
1716  else
1717  next1 <= wait_for_event; --I don't believe it should get here.
1718  end if;
1719 
1720  ctrl_code <= dbg_trlr_ld_last_o;
1721 
1724 
1725  when dbg_bad_l1ID =>
1726  next1 <= dbg_header_load;
1727  ctrl_code <= dbg_bad_l1ID_o;
1728 
1729 
1730 
1731 
1732  -- if (current_chan = num_chan) then
1733  -- next1 <= trailer_build;
1734  -- else
1735  -- next1 <= finish_reading;
1736 
1737 
1740  when start_empty_pkt =>
1741  next1 <= header_build;
1742  ctrl_code <= start_empty_pkt_o;
1743 
1744 
1749  -- ! If the flag is set when the next event has a complete l1id mismatch, then a resync is attempted by going back to the first channel and waiting for the
1751  when attempt_resync =>
1752  next1 <= await_resync;
1753 
1754  ctrl_code <= attempt_resync_o;
1758  when await_resync =>
1759  next1 <= idle_state;
1760 
1761  ctrl_code <= await_resync_o;
1762 
1768 
1769  when dbg_wait_for_hdr =>
1770  next1 <= check_error;
1771 
1772  ctrl_code <= dbg_wait_for_hdr_o;
1773 
1775  when others => next1 <= wait_for_event; ctrl_code <=wait_for_event_o;
1776  end case;
1777  end process;
1778 
1780 
1782 -- next_state <= wait_for_event when (reset = '1') else next1;
1783  next_state <= wait_for_event when ((reset = '1') or (wdog_overflow_i = '1')) else next1;
1784 
1785  --////////////////////////////////////////////////////////////////
1786  -- END of State Machine
1787  --////////////////////////////////////////////////////////////////
1788 
1789 
1790 -- chan_timeout <= ctrl_code(34);
1791  chan_pointer_reset <= ctrl_code(21); --resets the input mux pointer - it could also be reset with ctrl_code(13) - load header
1792  sel_corr_trailer <= ctrl_code(20);
1793  inc_corr_counter <= ctrl_code(19);
1794  clr_chan_len_cnt <= ctrl_code(18);
1795  clr_build_flag <= ctrl_code(17);
1796  set_build_flag <= ctrl_code(16);
1797  fifo_s_tvalid <= ctrl_code(15);
1798  fifo_s_tlast <= ctrl_code(14);
1799  load_hdr_reg <= ctrl_code(13);
1800  hdr_reg_valid <= ctrl_code(12);
1801  poll <= ctrl_code(11);
1802  inc_chan <= ctrl_code(10);
1803  load_last_chan <= ctrl_code(9);
1804  sel_packet_header <= ctrl_code(8);
1805  sel_packet_header_2 <= ctrl_code(7);
1806  sel_packet_trailer <= ctrl_code(6);
1807  trailer_crc20_calc <= ctrl_code(5);
1808  trailer_crc20_reset <= ctrl_code(4);
1809 
1810  pet_timer <= ctrl_code(3);
1811 
1812  hdr_out_crc9_start <= ctrl_code(2);
1813  chan_trailer_crc20_calc <= ctrl_code(1);
1814  chan_trailer_crc20_reset <= ctrl_code(0);
1815 
1816 ----------------------------------------------------------------------------------------
1817 -- end of state machine
1818 -----------------------------------------------------------------------------------------
1819 --at the end of the first event read, the leader becomes another follower (follows the lowest priority event handler)
1820 process (clock) begin
1821  if rising_edge (clock) then
1822  if (reset = '1') then
1823  lead_follow_b_reg <= lead_follow_b;
1824  elsif (current_state = trailer_mux) then
1825 --temporarily disable lead-follow
1826 -- lead_follow_b_reg <= '0';
1827  lead_follow_b_reg <= '1';
1828  end if;
1829  end if;
1830 end process;
1831 
1832 BCN <= master_header(11 downto 0);
1833 L1ID <= master_header(35 downto 12);
1834 ECRID <= master_header(43 downto 36);
1835 ORBIT <= master_header(59 downto 44);
1836 
1837 
1838 
1839 
1840 
1841 --sequence <= x"555";
1842 h_sequence <= header_sequence;
1843 --pkt_type <= x"A";
1844 pkt_type <= header_type;
1845 --version <= "001";
1846 --header_crc <= "000000000";
1847 
1848 --These are bits 7 & 6 of the first header word.
1849 --"00" => TOB
1850 --"10" => Raw (bulk)
1851 --"11" => Debug
1852 
1853 --tob_stream_id <= x"00";
1854 
1855 
1856 
1857 --changing header_reg to contain the TTC header rather than the channel header
1858  process (clock) begin
1859  if rising_edge (clock) then
1860  if load_hdr_reg = '1' then
1861 -- header_reg <= s_tdata;
1862  header_reg_0(7 downto 0) <= tob_stream_id;
1863  header_reg_0(19 downto 8) <= BCN;
1864  header_reg_0(28 downto 20) <= (others => '0'); --header_crc; --crc is not ready when load_hdr_reg occurs
1865  header_reg_0(31 downto 29) <= version;
1866  header_reg_1(23 downto 0) <= L1ID;
1867  header_reg_1(31 downto 24) <= ECRID;
1868  header_reg_2(3 downto 0) <= pkt_type;
1869  header_reg_2(15 downto 4) <= h_sequence;
1870  header_reg_2(31 downto 16) <= ORBIT;
1871  else
1872  header_reg_0 <= header_reg_0;
1873  header_reg_1 <= header_reg_1;
1874  header_reg_2 <= header_reg_2;
1875  end if;
1876  end if;
1877  end process;
1878 -- read the ttc header fifo and load the header reg.
1879 header_read_en <=load_hdr_reg;
1880 L1ID_ttc_hreg <= header_reg_1(23 downto 0);
1881 ECRID_ttc_hreg <= header_reg_1(31 downto 24);
1882 L1ID_ttc_32_reg <= header_reg_1(31 downto 0); --this is the 32-bit L1ID
1883 L1ID_ttc_32_reg_out <= header_reg_1(31 downto 0);
1884 BCID_reg <= header_reg_0(19 downto 8);
1885 
1886 --compare the TTC header L1A to the channel header L1A
1887 --(may need to compare master_header to s_tdata it bring in 1 cyc earlier)
1888 
1889 
1890 --changing l1ID comparisons to be full 32-bit values----------------
1891 --L1ID_eq <= '1' when ((L1ID = s_tdata(55 downto 32)) or (TTC_ignore = '1')) else '0'; --value based upon fifo output
1892 --L1ID_reg_eq <= '1' when ((s_tdata(55 downto 32) = header_reg_1(23 downto 0)) or (TTC_ignore = '1')) else '0'; --value based upon registered ttc header value
1893 
1894 L1ID_eq <= '1' when (((ECRid & L1ID) = s_tdata(63 downto 32)) or (TTC_ignore = '1')) else '0'; --value based upon fifo output
1895 L1ID_reg_eq <= '1' when ((s_tdata(63 downto 32) = L1ID_ttc_32_reg(31 downto 0)) or (TTC_ignore = '1')) else '0'; --value based upon registered ttc header value
1896 L1ID_reg_lt <= '1' when ((s_tdata(63 downto 32) < L1ID_ttc_32_reg(31 downto 0)) and (TTC_ignore = '0')) else '0'; --packet l1id less than current event l1id - old packet
1897 --L1ID_reg_gt <= '1' when ((s_tdata(63 downto 32) > L1ID_ttc_32_reg(31 downto 0)) or (TTC_ignore = '1')) else '0'; --and (L1ID_ttc_32_reg /= 32x"0") else '0'; --packet l1id greater than current event l1id - future packet unless TTC l1id just rolled over to 0
1898  --perhaps header_mark = 1 should also be checked here, but these signals shouldn't be used at other times
1899 --L1ID_reg_gt <= '1' when ((s_tdata(63 downto 32) <= L1ID_ttc_32_reg(31 downto 0) + 16) or (TTC_ignore = '1')) else '0'; --and (L1ID_ttc_32_reg /= 32x"0") else '0'; --packet l1id greater than current event l1id - future packet unless TTC l1id just rolled over to 0
1900 --"greater Than" is limited to meaning Greater Than but not by more than 4. If the L1ID mismatch is > 4, then something else is wrong
1901 L1ID_reg_gt <= '1' when (((s_tdata(63 downto 32) > L1ID_ttc_32_reg(31 downto 0)) and (s_tdata(63 downto 32) <= L1ID_ttc_32_reg(31 downto 0) + 4)) and (TTC_ignore = '0')) and (L1ID_ttc_32_reg /= 32x"0") else '0'; --packet l1id greater than current event l1id - future packet unless TTC l1id just rolled over to 0
1902 
1903 
1904 Process(clock) begin
1905  if rising_edge (clock) then
1906  if (reset = '1') then
1907  ttc_rollover_sig <= '0';
1908  elsif (ECRid & l1id) < l1id_ttc_32_reg then
1909  ttc_rollover_sig <= '1';
1910  else
1911  ttc_rollover_sig <= '0';
1912  end if;
1913  end if;
1914 end process;
1915 
1916 
1917 Process(clock) begin
1918  if rising_edge (clock) then
1919  if (reset = '1') then
1920  ttc_rollover_reg <= '0';
1921  else
1922  ttc_rollover_reg <= ttc_rollover_sig;
1923  end if;
1924  end if;
1925 end process;
1926 
1927 ttc_rollover <= ttc_rollover_sig and not ttc_rollover_reg;
1928 
1929 --BCID_mismatch <= '1' when ((BCN /= s_tdata(19 downto 8)) and (load_hdr_reg = '1')) else '0'; --one cycle pulse to feed counter
1930 BCID_mismatch <= '1' when ((BCID_reg /= s_tdata(19 downto 8)) and (poll_chan = '1')) else '0'; --one cycle pulse to feed counter
1931 
1932 
1933 --this is a pipeline bit to ease timing from the mux_pipr through the trailer flag logic
1934 process (clock) begin
1935  if rising_edge (clock) then
1936  L1ID_eq_pipe <= L1ID_reg_eq;
1937  end if;
1938  end process;
1939 
1940 
1941 
1942 with rod_slot select
1943  rod_number <= "00" when '1', --slot-1
1944  "01" when '0', --slot-2
1945  "00" when others;
1946 
1947 -- rod_number <= "01" when '1', --slot-1
1948 -- "10" when '0', --slot-2
1949 -- "01" when others;
1950 
1951 
1952 --rod_number <= "0001";
1953 --rod_link_error_map <= "000000000000";
1954 --rod_error_map <= "0000000";
1955 --fivet0 <= "00000";
1956 
1957 
1958 
1959 
1960 --event_trailer <= trailer_crc20 & fivet0 & rod_error_map & rod_link_error_map & rod_number & pkt_len_cnt_dly;
1961 event_trailer <= trailer_crc20 & lmem & '0' & rod_error_map & rod_link_error_map & efex_shelf_num & rod_number & pkt_len_cnt_dly;
1962 
1963 ------corrective trailer flags ---------
1964 process(clock) begin
1965  if rising_edge (clock) then
1966  if (current_state = continue_reading) then --continue_reading was chosen as the sample state, but an earlier sample may be required if a CT is to be asserted on a timeout
1967  corr_trail_chan <= current_chan;
1968  else
1969  corr_trail_chan <= corr_trail_chan;
1970  end if;
1971  end if;
1972 end process;
1973 
1974 
1975 process(clock) begin
1976  if rising_edge (clock) then
1977  if crc20_err = '1' then
1978  crc20_err_chan <= corr_trail_chan;
1979  end if;
1980  end if;
1981 end process;
1982 
1983 process(clock) begin
1984  if rising_edge (clock) then
1985  if (reset = '1') or (sel_corr_trailer = '1') or (chan_trailer_crc20_reset = '1') then --chan_trailer_crc20_reset was added in as belt and braces after the sel_corr_trailer was missed in some cases
1986  corr_trailer_len_flag <= '0';
1987  elsif (chan_len_error = '1') and (s_tlast_del2 = '1') then
1988  corr_trailer_len_flag <= '1';
1989  end if;
1990  end if;
1991 end process;
1992 process(clock) begin
1993  if rising_edge (clock) then
1994  if (reset = '1') or (sel_corr_trailer = '1') or (chan_trailer_crc20_reset = '1') then
1995  corr_trailer_pe_flag <= '0';
1996  elsif (crc20_err = '1') and (s_tlast_del2 = '1') then
1997  corr_trailer_pe_flag <= '1';
1998  end if;
1999  end if;
2000 end process;
2001 
2002 
2008 --corr_trailer <= chan_trailer_crc20 & "000000" & "100000" & x"0000" & corrected_length;
2009 --corr_trailer <= chan_trailer_crc20 & "000000" & "100000" & x"00" & shelf & current_chan(3 downto 0) & corrected_length;
2010 corr_trailer <= chan_trailer_crc20 & "000000" & "10" & corr_trailer_pe_flag & corr_trailer_len_flag & "00" & x"00" & shelf & corr_trail_chan(3 downto 0) & corrected_length;
2011 
2012 --mux to load event fifo with event_header, event_trailer, or event_data
2013 --note that sel_packet_trailer is also used to zero-out the crc field when calculating the event trailer crc
2014 --both sel_packet_trailer and sel_corr_trailer occur when inserting a corrective trailer into the last channel,while calculated the event trailer crc
2015 --perhaps another revision should have a dedicated control for zero'ing the crc field in the event trailer crc block.
2016  evnt_sel(3) <= sel_packet_header;
2017  evnt_sel(2) <= sel_packet_header_2;
2018  evnt_sel(1) <= sel_packet_trailer;
2019  evnt_sel(0) <= sel_corr_trailer;
2020 
2021  with evnt_sel select
2022  fifo_s_tdata <= header_reg_1 & header_reg_0(31 downto 29) & header_crc & header_reg_0(19 downto 0) when "1000",
2023  x"00000000" & header_reg_2 (31 downto 0)when "0100",
2024  event_trailer when "0010",
2025  corr_trailer when "0001",
2026  -- corr_trailer when "0011", --both sel_packet_trailer and sel_corr_trailer occur when inserting a corrective trailer into the last channel, just before the event trailer
2027  s_tdata when "0000",
2028  s_tdata when others;
2029 
2030 
2031 
2032  -- fifo_s_tdata <= x"b0f1faceb1100b44" when "100",
2033  -- x"b0f2faceb1100b44" when "010",
2034  -- x"e0f0faceb1100b44" when "001",
2035  -- s_tdata when "000",
2036  -- s_tdata when others;
2037 
2038 
2039 
2040 
2041 --Last_chan generation
2042 
2043 --process (clock) begin
2044 -- if rising_edge (clock) then
2045 -- if load_last_chan = '1' then
2046 -- if (current_chan = x"0") then last_chan <= x"b";
2047 -- else
2048 -- last_chan <= (current_chan-1);
2049 -- end if;
2050 -- end if;
2051 -- end if;
2052 --end process;
2053 
2054 --Next_chan generation
2055 process (clock) begin
2056  if rising_edge (clock) then
2057  if (reset = '1') then
2058 -- next_chan <= x"1";
2059  next_chan <= (first_chan + 1);
2060  elsif inc_chan = '1' then
2061  if (next_chan = num_chan) then
2062 -- next_chan <= X"0";
2063  next_chan <= first_chan;
2064  else
2065  next_chan <= (next_chan + 1);
2066  end if;
2067  end if;
2068  end if;
2069 end process;
2070 
2071 
2072 --TOB timeout function
2073 timeout : tob_timeout
2074  Port map ( clock => clock,
2075  reset => reset,
2076  start_timer => pet_timer,
2077  stop_timer => stop_timeout,
2078 -- set_time_1 => x"0400", --128 expected * 2 worst case * 4 for 160MHz
2079 -- set_time_n => x"0030",
2080  set_time_1 => timeout_1_val,
2081  set_time_n => timeout_n_val,
2082  timeout_1 => timeout_1_raw,
2083  timeout_n => timeout_n_raw,
2084  counter_out => timeout_counter,
2085  run_out => timeout_run
2086  );
2087 timeout_1 <= (timeout_1_raw and not tob_timeout_1_disable);
2088 timeout_n <= (timeout_n_raw and not tob_timeout_n_disable);
2089 
2090 --finished_lc <= '1' when (current_state = add_corr_trlr_lc) else '0';
2091 --stop_timeout <= s_tvalid and chan_enable_del and not finished_lc;
2092 stop_timeout <= s_tvalid and chan_enable_del and not pet_timer;
2093 
2094 --build flag (remembers if an event packet header was built)
2095 process (clock) begin
2096  if rising_edge (clock) then
2097  if (reset = '1') or (clr_build_flag = '1') then
2098  build_flag <= '0';
2099  elsif (set_build_flag = '1') then
2100  build_flag <= '1';
2101  else
2102  build_flag <= build_flag;
2103  end if;
2104  end if;
2105  end process;
2106 
2107 --last chan read flag: the last channel has been read out
2108 ----This looks like a problem because it only gets cleared on reset or when adding a corrective trailer
2109 -------and, it's not even add_corr_trailer_lc (last channel)
2110 
2111 process (clock) begin
2112  if rising_edge (clock) then
2113  if (reset = '1') or (current_state = add_corr_trailer) or (current_state = add_corr_trlr_lc) or (current_state = trailer_mux) then
2114  last_chan_read <= '0';
2115  elsif (current_state = continue_reading) and (current_chan = num_chan) then
2116  last_chan_read <= '1';
2117  else
2118  last_chan_read <= last_chan_read;
2119  end if;
2120  end if;
2121 end process;
2122 
2123  process (clock) begin
2124  if rising_edge (clock) then
2125  if (reset = '1') or (current_state = wait_for_event) then
2126  any_chan_read <= '0';
2127  elsif (current_state = continue_reading) and (current_state = start_reading) then
2128  any_chan_read <= '1';
2129  else
2130  any_chan_read <= any_chan_read;
2131  end if;
2132  end if;
2133 end process;
2134 
2135 
2136 
2137 
2138 -->a delayed chan_enable signal is created because of the delay in evaluating crc20 before deciding to invoke corrective trailer processing
2139 --> that decision is taken in the cycle following the channel increment, so it is necessary to remember if the channel is enabled and the crc20 is valid
2140 
2141 process (clock) begin
2142  if rising_edge (clock) then
2143  if (reset = '1') then
2144  chan_enable_del <= '0';
2145  else
2146  chan_enable_del <= chan_enable;
2147  end if;
2148  end if;
2149 end process;
2150 
2151 --empty_out is set if this queue is empty (used for multiprocessor)
2152 --process (clock) begin
2153 -- if rising_edge (clock) then
2154 -- if (reset = '1') or ((tob_data_count <= x"0256")) then
2155 -- empty_out <= '1';
2156 -- else
2157 -- empty_out <= '0';
2158 -- end if;
2159 -- end if;
2160 --end process;
2161 
2162 ----------------------------------
2163 --channel length counter
2164 ----------------------------------
2165 -->this should be payload length; excluding header and trailer
2166 -->the headers and trailers can be excluded by making sure they are not selected are not selected
2167 -->the trailer could be excluded by using fifo_tvalid and not fifo_tlast and the count.
2168 -->tlast can be used to capture the declared length and compare it to the counter
2169 
2170 
2171 process (clock) begin
2172  if rising_edge (clock) then
2173  -- if (reset = '1') or (inc_chan = '1') then
2174  -- if (reset = '1') or (clr_chan_len_cnt = '1') then
2175  if (reset = '1') or (clr_chan_len_cnt = '1') or (s_tlast_del2 = '1') then
2176  chan_len_cnt <= "000000000000";
2177  elsif ((fifo_s_tvalid = '1') and (s_tlast = '0') and (evnt_sel = "000") and (fifo_s_tready = '1'))then -- or (inc_len_counters='1') then
2178  chan_len_cnt <= (chan_len_cnt + 2);
2179  end if;
2180  end if;
2181 end process;
2182 ---length error bit
2183 process (clock) begin
2184  if rising_edge (clock) then
2185 -- if (reset = '1') or (sel_packet_trailer = '1') then
2186 -- if (reset = '1') or (chan_len_error = '1') then
2187  if (reset = '1') or (s_tlast_del2 = '1') or ((s_tlast = '1') and (chan_len_cnt = s_tdata(11 downto 0))) then
2188  chan_len_error <= '0';
2189  -- elsif (s_tlast = '1') and (chan_len_cnt = s_tdata(11 downto 0)) then
2190  -- chan_len_error <= '0';
2191 
2192  elsif (s_tlast = '1') and (chan_len_cnt /= s_tdata(11 downto 0)) then
2193  chan_len_error <= '1';
2194 
2195  else
2196  chan_len_error <= chan_len_error;
2197  end if;
2198  end if;
2199  end process;
2200 
2201 
2202 --> corrected length block is used when forming the corrective trailer
2203 process (clock) begin
2204  if rising_edge (clock) then
2205  -- if (reset = '1') or (inc_chan = '1') then
2206  if (reset = '1') or (clr_chan_len_cnt = '1') then -- or (s_tlast_del2 = '1') then
2207  corrected_length <= x"0000";
2208  elsif ((fifo_s_tvalid = '1') and (s_tlast = '0') and (evnt_sel = "000") and (fifo_s_tready = '1')) or (inc_corr_counter='1') then
2209 
2210  corrected_length <= (corrected_length + 2);
2211  end if;
2212  end if;
2213 end process;
2214 
2215 
2216 
2217 -----------------------------
2218 --packet length counter
2219 -------------------------------
2220 --packet length counter payload (including padding) excluding header and trailer
2221 --the counter could be 11-bits instead of 12 because the LSB is always 0 due to inc by 2.
2222 --it is initialised to the value 2 because the last incoming word will not be counted (s_tlast = 0). this allows the count to end 1 cycle early,
2223 --which allows the crc calsulation to begin early
2224 --pkt_len_cnt(0) <= '0';
2225 process (clock) begin
2226  if rising_edge (clock) then
2227  if (reset = '1') or (sel_packet_header = '1') then
2228  pkt_len_cnt(15 downto 0) <= x"0002";
2229 -- elsif (fifo_s_tvalid = '1') and (fifo_s_tready = '1') and (s_tlast = '0') and (sel_packet_header = '0') and (sel_packet_header_2 = '0') and (fifo_s_tlast = '0') then
2230  elsif (fifo_s_tvalid = '1') and (fifo_s_tready = '1') and (sel_packet_header = '0') and (sel_packet_header_2 = '0') and (fifo_s_tlast = '0') then
2231  pkt_len_cnt <= (pkt_len_cnt + 2);
2232  pkt_len_cnt_dly <= pkt_len_cnt;
2233  else
2234  pkt_len_cnt <= pkt_len_cnt;
2235  end if;
2236  end if;
2237 end process;
2238 
2239 
2240 
2241 
2242 
2243 
2244 ----packet length counter (excluding padding)
2245 --process (clock) begin
2246 -- if rising_edge (clock) then
2247 -- if (reset = '1') or (load_hdr_reg = '1') then
2248 -- pkt_len_cnt <= "000000000000";
2249 -- elsif (inc_chan = '1') then
2250 -- pkt_len_cnt <= (pkt_len_cnt + chan_len_cnt);
2251 -- end if;
2252 -- end if;
2253 --end process;
2254 
2255 
2256 -----------------------------------------------------------------------------------------------
2261 process (clock) begin
2262  if rising_edge (clock) then
2263  if (reset = '1') or (fifo_s_tlast = '1') then
2264  tob_pkt_active <= '0';
2265  elsif (sel_packet_header = '1') then --assume a tob packet is being started if the header is loadedinto the fifo (could also use poll)
2266  --elsif (load_hdr_reg = '1') then --(formerly load_hdr_reg, but ths is not necessarily the start of a packet)
2267  tob_pkt_active <= '1';
2268  else
2269  tob_pkt_active <= tob_pkt_active;
2270  end if;
2271  end if;
2272 end process;
2273 -------------------------------------------------------------------------------------------------
2274 
2275 
2276 -------------------------------------------------------------------------------------------------
2279 process (clock) begin
2280  if rising_edge (clock) then
2281  if (reset = '1') or (fifo_s_tlast = '1') then
2282  empty_pkt_active <= '0';
2283  elsif (set_empty_packet_build = '1') then
2284  empty_pkt_active <= '1';
2285  else
2286  empty_pkt_active <= empty_pkt_active;
2287  end if;
2288  end if;
2289 end process;
2290 
2291 -------------------------------------------------------------------------
2292 
2293 --channel input header crc check
2294 channel_header_crc : hdr_in_crc9
2295  Port map(
2296  clock => clock,
2297  -- crc_reset => load_hdr_reg, --connect to ld_hdr_reg in this level
2298  crc_reset => hdr_in_crc9_reset, --must reset after each channel - not just before the first channel
2299  s_tdata => s_tdata,
2300  crc_start => poll, --connect to poll in this level
2301  header_mismatch => chan_hdr_crc_err
2302  );
2303 
2304 hdr_in_crc9_reset <= s_tlast_del2 or reset;
2305 
2306 process (clock) begin
2307  if rising_edge (clock) then
2308  if (reset = '1') then
2309  hdr_crc_flag <= '0';
2310  else
2311  hdr_crc_flag <= chan_hdr_crc_err;
2312  end if;
2313  end if;
2314 end process;
2315 -- -------------------------------------------
2316 --event header crc generation
2317 -- -------------------------------------
2318 
2319 event_header_crc : event_hdr_crc9
2320  Port map (
2321  clock => clock,
2322  crc_reset => sel_packet_header_2,
2323  BCN => BCN,
2324  version => version,
2325  tob_stream_id => tob_stream_id,
2326 -- ECRID => ECRID,
2327 -- L1ID => L1ID,
2328  ECRID => ECRID_ttc_hreg,
2329  L1ID => L1ID_ttc_hreg,
2330 -- header_reg_0 : in STD_LOGIC_VECTOR (31 downto 0);
2331  header_reg_1 => header_reg_1,
2332  header_reg_2 => header_reg_2,
2333  crc_start => header_crc_start,
2334  load_hdr_reg => load_hdr_reg,
2335  CRC_out => header_crc,
2336  hdr_out_crc9_valid => hdr_out_crc9_valid
2337  );
2338 
2339 
2340 --header_crc_start <= header_fifo_valid and hdr_out_crc9_start;
2341 header_crc_start <= hdr_out_crc9_start;
2342 
2343 event_trailer_crc : event_trailer_crc20
2344  generic map(
2345  CRC20_G_Poly => CRC20_G_Poly,
2346  Nbits => 64,
2347  CRC_Width => 20,
2348  G_InitVal => x"fffff"
2349  )
2350  Port map(
2351  clock => clock,
2352  crc_reset => trailer_crc20_reset,
2353  CRC => trailer_crc20,
2354  Calc => trailer_crc20_calc,
2355  S_tdata => fifo_s_tdata,
2356  sel_packet_trailer => sel_packet_trailer
2357  );
2358 
2359 
2360 
2361 
2362 
2363 -- -------------------------------
2364 -- channel trailer crc 20 check
2365 -----------------------------------
2366 --in addition to checking the incoming crc20 on each channel,
2367 --this crc block is also used to calculate the crc to be used in the corrective trailer.
2368 
2369 --The input to the crc is muxed in order to provide the corr trailer when it is needed
2370 chan_crc_dmux_ctrl <= ((s_tlast_del2 and not s_tvalid) and (chan_crc20_err or chan_len_error)) or corr_trailer_pe_flag or corr_trailer_len_flag;
2371 chan_crc_dmux_data <= x"00000" & corr_trailer(43 downto 0);
2372 
2373  with chan_crc_dmux_ctrl select
2374  chan_crc_din <= s_tdata when '0',
2375  chan_crc_dmux_data when '1',
2376  s_tdata when others;
2377 
2378 
2379 chan_trailer_crc : event_trailer_crc20
2380  generic map(
2381  CRC20_G_Poly => CRC20_G_Poly,
2382  Nbits => 64,
2383  CRC_Width => 20,
2384  G_InitVal => x"fffff"
2385  )
2386  Port map(
2387  clock => clock,
2388  crc_reset => chan_trailer_crc20_reset,
2389  CRC => chan_trailer_crc20,
2390  Calc => chan_trailer_crc20_calc,
2391  -- S_tdata => s_tdata, --need to mux in corr trailer
2392  S_tdata => chan_crc_din,
2393  sel_packet_trailer => s_tlast
2394  );
2395 
2396 --proposed incoming crc20
2397  process (clock) begin
2398  if rising_edge (clock) then
2399  if s_tlast = '1' then
2400  proposed_crc20(19 downto 0) <= s_tdata(63 downto 44);
2401  end if;
2402  end if;
2403  end process;
2404 
2405 
2406 
2407 --compare generated vs proposed
2408 chan_crc20_err <= '1' when proposed_crc20 /= chan_trailer_crc20 else '0';
2409 
2410 
2411 
2412 --comparison is valid 2 cycles after s_tlast
2413 process (clock) begin
2414  if rising_edge (clock) then
2415  s_tlast_del <= s_tlast and s_tvalid; --adding in s_tvalid assures that this is a one cycle pulse
2416  s_tlast_del2 <= s_tlast_del;
2417  end if;
2418 end process;
2419 
2420 --process (clock) begin
2421 -- if rising_edge (clock) then
2422 -- if (s_tlast_pulse = '1') and (s_tlast = '0') then
2423 -- s_tlast_pulse <= '0';
2424 -- elsif s_tlast_pulse = '1' then --s_tlast_pulse is to assure that s_tlast_del and s_tlast_del2 are one cycle pulses
2425 -- s_tlast_del <= '0';
2426 -- else
2427 -- s_tlast_pulse <= s_tlast;
2428 -- s_tlast_del <= s_tlast;
2429 -- s_tlast_del2 <= s_tlast_del;
2430 -- end if;
2431 -- end if;
2432 --end process;
2433 
2434 
2435 --Chan_crc20_error flag for use in a counter/register to keep track of the number of errors
2436 --This flag lasts for only one pp_clk cycle
2437 --this counter is placed in the TOB_proc registers?
2438 crc20_err <= s_tlast_del2 and chan_crc20_err;
2439 
2440 crc9_err <= s_tlast_del2 and chan_hdr_crc_err;
2441 
2442 
2443 --timeout_error <= '1' when ((current_state = (idle_state or check_error)) and (timeout_1 = '1' or timeout_n = '1')) else'0';
2444 timeout_error <= '1' when (((current_state = idle_state) and (current_chan = first_chan) and (timeout_1 = '1'))
2445  or ((current_state = idle_state) and (current_chan /= first_chan) and (timeout_n = '1'))
2446  or ((current_state = eval_chan_crc20) and ((timeout_n = '1') and (current_chan = num_chan) and (tob_pkt_active = '1')))
2447  or ((current_state = check_error) and (timeout_n = '1')))
2448 
2449  else'0';
2450 dbg_timeout_error <= '1' when ((current_state = dbg_trail_build_3) and ((timeout_1 = '1') or (timeout_n = '1'))) else '0';
2451 timeout_err <= timeout_error;
2452 -----------------------------------------------------------------------------------
2453 
2454 -- ----------------------------------------
2455 -- event trailer error map generation
2456 -- --------------------------------------
2457 evnt_trailer_err_map : trailer_map
2458 
2459  generic map (
2460  jfex => jfex
2461  )
2462  Port map (
2463  pp_clock => clock,
2464  reset => trailer_crc20_reset, --temporary
2465 -- reset => fifo_s_tlast,
2466  current_chan => current_chan,
2467  chan_len_error => chan_len_error,
2468  chan_hdr_crc_err => chan_hdr_crc_err,
2469  chan_crc20_err => chan_crc20_err,
2470  L1ID_eq => L1ID_eq_pipe, --L1ID_reg_eq,
2471  chan_crc20_samp => s_tlast_del2,
2472  crc9_err_samp => s_tlast_del2,
2473  len_err_samp => s_tlast_del2,
2474  L1id_eq_samp => sel_packet_header_2,
2475  timeout_error => timeout_error,
2476  clear_map => load_last_chan,
2477  sel_corr_trailer => sel_corr_trailer,
2478  error_map => rod_link_error_map,
2479  lmem => LMEM,
2480  rod_err_map => rod_error_map,
2481  debug_pkt_module_map => open
2482  );
2483 
2484 
2485 
2486 
2487 
2488 
2489 -------------------------------------------------
2490 --register the declared channel length from s_tdata during trailer (trailer marker)
2491 --compare with the length computed above (without LSB's so as to ignore padding)
2492 --if these are not equal set an error flag
2493 --if there is no error, add the declared length to the packet length count
2494 -- if there is an error, then add the measured length to the packet count
2495 --I have proposed that we measure the actual payload length including the padding, which will
2496 --simplify this. In this case the packet length is just a counter of when tvalid is active, and
2497 --registered on a tlast.
2498 
2499 
2500 poll_chan <= poll;
2501 nxt_chan <= inc_chan;
2502 --empty_stat <= empty_out;
2503 hdr_match <= match_out;
2504 s_tready <= fifo_s_tready;
2505 
2506 
2507 
2508 
2509 
2510 --the end
2511 
2512 
2513 
2514 --current_chan is broadcast from the channel mux to say what channel is active at any time.
2515 
2516 --
2517 --the queue_active signal is set when the packet receive operation is initiated and is cleared when the last word of a packet has been read.
2518 --the packet receive operation can be triggered when the header register is valid, and the header_marker is active.
2519 --it is triggered by bringing poll_chan high for one cycle.
2520 
2521 
2522 
2523 --queue_active
2524 
2525 
2526 
2527 --hdr_reg_valid is set when the header register is loaded to indicate that the register contains a current and valid value.
2528 --the header register needs to remain unchanged until all of the input channels have been polled to be sure all event fragments
2529 --have been collected.
2530 
2531 --inorder to keep track of whether all channels have been polled, a record must be kept of the channel that was active
2532 --when the header register was loaded when that channel is reached again, the the header register may be reloaded, or the
2533 --hdr_reg_valid signal must be cleared
2534 
2535 --hdr_match is set when the header_marker is true and the header_register matches the header data.
2536 --hdr_match
2537 
2538 ---------------------------------------------------------------------------------------------------------------
2539 --------------------------- debug stream section -----------------------------------------------------------
2540 ---------------------------------------------------------------------------------------------------------------
2541 ---------------------------------------------------------------------------------------------------------------
2542 set_empty_packet_build <= ctrl_code(33);
2543 set_bad_l1id_flag <= ctrl_code(32);
2544 dbg_s_tvalid <= ctrl_code(31);
2545 dbg_s_tlast <= ctrl_code(30);
2546 dgb_crc9_reset <= ctrl_code(29);
2547 dbg_crc9_calc <= ctrl_code(28);
2548 sel_dbg_header <= ctrl_code(27);
2549 sel_dbg_trailer <= ctrl_code(26);
2550 dgb_crc20_reset <= ctrl_code(25);
2551 dbg_crc20_calc <= ctrl_code(24);
2552 dbg_LenCount_Ena <= ctrl_code(23);
2553 dbg_LenCount_Rst <= ctrl_code(22);
2554 
2555 
2556 --dbg_stream_id <= x"C0";
2557 --dbg_stream_id <= "11010001";
2558 --"11" => Debug
2559 --"01" => rod FPGA
2560 --"0001" => rod slot (temporarily hard wired)
2561 
2562 with rod_slot select
2563  dbg_stream_id <= x"DD" when '1',
2564  x"DE" when others;
2565 
2566 debug_fifo: event_builder_fifo
2567  port map(
2568 -- s_axis_tvalid => s_tvalid,
2569  s_axis_tvalid => dbg_s_tvalid,
2570  s_axis_tready => dbg_s_tready,
2571  s_axis_aresetn => s_axis_aresetn,
2572  s_axis_aclk => clock,
2573  s_axis_tlast => dbg_s_tlast,
2574 
2575 -- s_axis_tuser(1) => s_header_mark,sel_dbg_header
2576 -- s_axis_tuser(0) => dbg_s_tlast,
2577  s_axis_tuser(1) => sel_dbg_header,
2578  s_axis_tuser(0) => sel_dbg_trailer,
2579 
2580 -- s_axis_tdata => s_tdata,
2581  s_axis_tdata => dbg_s_tdata,
2582 
2583  m_axis_tvalid => dbg_m_tvalid_i,
2584  m_axis_tlast => dbg_m_tlast_i,
2585  m_axis_tready => dbg_m_tready,
2586  m_axis_tuser(1) => dbg_m_header_marker_i,
2587  m_axis_tuser(0) => dbg_m_tail_marker_i,
2588  m_axis_tdata => dbg_m_tdata_i,
2589 
2590  -- axis_data_count => debug_fifo_level,
2591  axis_wr_data_count => debug_fifo_level,
2592  axis_rd_data_count => open
2593  );
2594 
2595 
2596 --mux to load debug fifo with debug_stream_header, corrective_trailer, or channel_data
2597  dbg_sel(1) <= sel_dbg_header;
2598  dbg_sel(0) <= sel_dbg_trailer;
2599 
2600  with dbg_sel select
2601  dbg_s_tdata <= dbg_header_reg_tmp when "10",
2602  dbg_corr_trailer when "01",
2603  s_tdata when "00",
2604  s_tdata when others;
2605 
2606 
2607 
2608 dbg_header_reg_tmp(7 downto 0) <= dbg_stream_id;
2609 --dbg_header_reg_tmp(19 downto 8) <= x"000";
2610 dbg_header_reg_tmp(19 downto 8) <= BCID_reg;
2611 dbg_header_reg_tmp(28 downto 20) <= dbg_hdr_crc;
2612 dbg_header_reg_tmp(31 downto 29) <= version;
2613 --dbg_header_reg_tmp(63 downto 32) <= x"00000000";
2614 dbg_header_reg_tmp(63 downto 32) <= L1ID_ttc_32_reg;
2615 
2616 --changing header_reg to contain the Debug Stream ID and 000 in the CRC position
2617  process (clock) begin
2618  if rising_edge (clock) then
2619  if dbg_crc9_calc = '1' then
2620  dbg_header_reg(7 downto 0) <= dbg_stream_id;
2621  -- dbg_header_reg(19 downto 8) <= x"000";
2622  dbg_header_reg(19 downto 8) <= BCID_reg;
2623  dbg_header_reg(28 downto 20) <= dbg_hdr_crc;
2624  dbg_header_reg(31 downto 29) <= version;
2625  -- dbg_header_reg(63 downto 32) <= x"00000000";
2626  dbg_header_reg(63 downto 32) <= L1ID_ttc_32_reg;
2627  end if;
2628  end if;
2629  end process;
2630 
2631 
2632 --changing header_reg to contain the Debug Stream ID and 000 in the CRC position
2633  -- process (clock) begin
2634  -- if rising_edge (clock) then
2635  --
2636  -- dbg_corr_trailer(19 downto 16) <= x"000";
2637  -- dbg_corr_trailer(28 downto 20) <= dbg_hdr_crc;
2638  -- dbg_corr_trailer(31 downto 29) <= version;
2639  -- dbg_corr_trailer(63 downto 32) <= x"00000000";
2640 --
2641  -- end if;
2642  -- end process;
2643 --although this is labelled dbg_corr_trailer, it is the normal debug packet trailer (not corrective)
2644 dbg_corr_trailer(15 downto 0) <= dbg_LenCount & '0';
2645 --dbg_corr_trailer(19 downto 16) <= current_chan(3 downto 0);
2646 dbg_corr_trailer(17 downto 16) <= rod_number; --rod module number
2647 dbg_corr_trailer(19 downto 18) <= efex_shelf_num; --shelf numeber
2648 dbg_corr_trailer (31 downto 20) <= dbg_link_error_map; --link error map
2649 dbg_corr_trailer (38 downto 32) <= dbg_error_map; --rod error map
2650 --dbg_corr_trailer (38 downto 32) <= "1011111"; --rod error map
2651 dbg_corr_trailer (39) <= '0';
2652 dbg_corr_trailer (43 downto 40) <= dbg_LMEM;
2653 dbg_corr_trailer (63 downto 44) <= dbg_trailer_CRC; --20b trailer CRC
2654 
2655 
2656 --dbg_crc_in_flip <= s_tdata(31 downto 29) & "000000000" & s_tdata(19 downto 0) & s_tdata(63 downto 32);
2657 --dbg_crc9_in_flip <= version & "000000000" & x"000" & dbg_stream_id & x"00000000";
2658 dbg_crc9_in_flip <= version & "000000000" & BCID_reg & dbg_stream_id & L1ID_ttc_32_reg;
2659 
2660 with dbg_s_tvalid select
2661  dbg_crc20_in_flip <= dbg_s_tdata(31 downto 0) & dbg_s_tdata(63 downto 32) when '1',
2662  dbg_corr_trailer(31 downto 0) & x"00000" & dbg_corr_trailer(43 downto 32) when '0',
2663  dbg_s_tdata(31 downto 0) & dbg_s_tdata(63 downto 32) when others;
2664 
2665 
2666 -----------------------------------------------
2667 --Debug Packet Counter
2668 -----------------------------------------------
2669 process (clock) begin
2670  if rising_edge (clock) then
2671  if dbg_pkt_count_reset = '1' then
2672  dbg_pkt_count_i <= (others => '0');
2673  elsif ((dbg_m_tlast_i and dbg_m_tvalid_i) = '1') and (dbg_pkt_count_i < x"ffffffff") then
2674  dbg_pkt_count_i <= (dbg_pkt_count_i + 1);
2675  else
2676  dbg_pkt_count_i <= dbg_pkt_count_i;
2677  end if;
2678  end if;
2679 end process;
2680 
2681 dbg_pkt_count <= dbg_pkt_count_i;
2682 
2683 
2684 
2685 
2686 
2687 
2688 -------------------------------------------------
2689 --incoming debug packet length counter
2690 -------------------------------------------------
2691 process (clock) begin
2692  if rising_edge (clock) then
2693  if dbg_LenCount_Rst = '1' then
2694  dbg_chan_LenCount <= x"FFE"; --set to "-2 " to make payload only
2695  elsif dbg_LenCount_Ena = '1' then
2696  dbg_chan_LenCount <= dbg_chan_LenCount + x"2";
2697  end if;
2698  end if;
2699  end process;
2700 ---length error bit
2701 process (clock) begin
2702  if rising_edge (clock) then
2703 
2704  if (reset = '1') or (dbg_LenCount_Rst = '1') or ((s_tlast = '1') and (s_tvalid = '1') and (dbg_chan_lencount = dbg_s_tdata(11 downto 0))) then
2705  dbg_chan_len_error <= '0';
2706  elsif (s_tlast = '1') and (s_tvalid = '1') and (dbg_chan_lencount /= dbg_s_tdata(11 downto 0)) then
2707  dbg_chan_len_error <= '1';
2708  else
2709  dbg_chan_len_error <= dbg_chan_len_error;
2710  end if;
2711  end if;
2712  end process;
2713 
2714 
2715 
2716 --------------------------------------------
2717 --outgoing debug packet header crc generation
2718 -----------------------------------------------
2719 
2720 dbg_crc9_gen : CRC
2721  generic map (
2722  Nbits => 64,
2723  CRC_Width => 9)
2724  port map (
2725 
2726  CRC => dbg_hdr_CRC,
2727  Calc => dbg_crc9_calc,
2728  Clk => clock,
2729  DIn => dbg_crc9_in_flip,
2730  Reset => dgb_crc9_reset
2731  );
2732 
2733 
2734 --------------------------------------------
2735 --outgoing debug packet trailer crc generation
2736 -----------------------------------------------
2737 dbg_crc20_gen : CRC
2738  generic map (
2739  Nbits => 64,
2740  CRC_Width => 20,
2741  -- G_Poly => x"c1acf",
2742  -- G_Poly => x"8349f",
2743  G_Poly => CRC20_G_Poly,
2744  G_InitVal => x"fffff")
2745  port map (
2746 
2747  CRC => dbg_trailer_CRC,
2748  Calc => dbg_crc20_calc,
2749  Clk => clock,
2750  DIn => dbg_crc20_in_flip,
2751  Reset => dgb_crc20_reset
2752  );
2753 
2754 -------------------------------------------------
2755 --outgoing Debug Packet trailer Length Counter
2756 --------------------------------------------------
2757  process (clock) begin
2758  if rising_edge (clock) then
2759  if dbg_LenCount_Rst = '1' then
2760  dbg_LenCount <= (others => '0');
2761  elsif dbg_LenCount_Ena = '1' then
2762  dbg_LenCount <= dbg_LenCount + '1';
2763  end if;
2764  end if;
2765  end process;
2766 
2767 
2768 
2769 -- ----------------------------------------
2770 -- event trailer error map generation
2771 -- --------------------------------------
2772 dbg_trailer_err_map : trailer_map
2773 
2774  generic map (
2775  jfex => jfex
2776  )
2777  Port map (
2778  pp_clock => clock,
2779  reset => dgb_crc20_reset, --temporary
2780 -- reset => fifo_s_tlast,
2781  current_chan => current_chan,
2782  chan_len_error => dbg_chan_len_error,
2783  chan_hdr_crc_err => chan_hdr_crc_err,
2784  chan_crc20_err => chan_crc20_err,
2785  L1ID_eq => L1ID_eq_pipe, --L1ID_reg_eq,
2786  chan_crc20_samp => s_tlast_del2,
2787  crc9_err_samp => s_tlast_del2,
2788  len_err_samp => s_tlast_del2,
2789  L1id_eq_samp => set_bad_l1id_flag, -- or sel_dbg_header,
2790  timeout_error => dbg_timeout_error,
2791  clear_map => dgb_crc20_reset,
2792  sel_corr_trailer => sel_corr_trailer,
2793  error_map => open, --dbg_link_error_map,
2794  lmem => dbg_LMEM,
2795  rod_err_map => dbg_error_map,
2796  debug_pkt_module_map => dbg_link_error_map
2797  );
2798 
2799 
2800 --l1id_mismatch <= set_bad_l1id_flag;
2801 
2802 l1id_mismatch <= poll_chan and not L1ID_reg_eq;
2803 
2804 
2805 
2806 
2807 
2808 
2809 -----------------------------------------------------------------------------------------------------
2810 ----------output mux ---------------------------------------------
2811 ----------------------------------------------------------------------------------
2812 
2813 
2814  with tobsel select
2815  m_tdata_i <= dbg_m_tdata_i when '0', --debug fifo output
2816  tob_m_tdata_i when '1', --event fifo output
2817  tob_m_tdata_i when others;
2818 with tobsel select
2819  m_tvalid_i <= dbg_m_tvalid_i when '0', --debug fifo output
2820  tob_m_tvalid_i when '1', --event fifo output
2821  tob_m_tvalid_i when others;
2822 
2823 with tobsel select
2824  m_tlast_i <= dbg_m_tlast_i when '0', --debug fifo output
2825  tob_m_tlast_i when '1', --event fifo output
2826  tob_m_tlast_i when others;
2827 
2828 with tobsel select
2829  m_header_marker_i <= dbg_m_header_marker_i when '0', --debug fifo output
2830  tob_m_header_marker_i when '1', --event fifo output
2831  tob_m_header_marker_i when others;
2832 
2833 with tobsel select
2834  m_tail_marker_i <= dbg_m_tail_marker_i when '0', --debug fifo output
2835  tob_m_tail_marker_i when '1', --event fifo output
2836  tob_m_tail_marker_i when others;
2837 
2838 
2839  tob_m_tready <= tobsel and m_tready;
2840  dbg_m_tready <= not tobsel and m_tready;
2841 
2842 
2843 --process (clock) begin
2844 -- if rising_edge (clock) then
2845 -- if (reset = '1') or ((tobsel = '0') and (dbg_m_tlast_i = '1') and ((tob_m_header_marker_i = '1')and (tob_m_tvalid_i = '1'))) THEN
2846 -- tobsel <= '1';
2847 -- elsif (tobsel = '1') and (dbg_m_header_marker_i = '1')and ((tob_m_tlast_i = '1')or (tob_m_tvalid_i = '0')) then
2848 -- tobsel <= '0';
2849 -- end if;
2850 -- end if;
2851 -- end process;
2852 
2853 process (clock) begin
2854  if rising_edge (clock) then
2855  if (reset = '1') or ((tobsel = '0') and ((dbg_m_tlast_i = '1') or (dbg_m_tvalid_i = '0'))) then -- and ((tob_m_header_marker_i = '1')and (tob_m_tvalid_i = '1'))) THEN
2856  tobsel <= '1';
2857  elsif (tobsel = '1') and (dbg_m_tvalid_i = '1') and ((tob_m_tlast_i = '1') or (tob_m_tvalid_i = '0')) then
2858  tobsel <= '0';
2859  -- else
2860  -- tobsel <= '1';
2861  end if;
2862  end if;
2863  end process;
2864 
2865 
2866  --generating the reference L1ID(0) for this ROD
2876 
2879 
2880 --this is just an XOR function
2881 process (event_sel(0), rod_slot)
2882 variable sel_bus : std_logic_vector(1 downto 0);
2883  begin
2884  sel_bus := event_sel(0) & rod_slot;
2885  case sel_bus is
2886  when "00" => -- slot = 2, therefore accept events for L1ID(0) = 0
2887  reference_lid_0 <= '0';
2888  when "01" => -- slot = 1, therefore accept events for L1ID(0) = 1
2889  reference_lid_0 <= '1';
2890  when "10" => --slot = 2, but sel opposite, therefore accept events for L1ID(0) = 1
2891  reference_lid_0 <= '1';
2892  when "11" =>
2893  reference_lid_0 <= '0';
2894  when others =>
2895  reference_lid_0 <= '0';
2896  end case;
2897 end process;
2898 
2899 
2900 
2901 --bad L1ID flag
2902 process (clock) begin
2903  if rising_edge (clock) then
2904  if (reset = '1') or (dbg_s_tlast = '1') then
2905  bad_l1id_flag <= '0';
2906  elsif set_bad_l1id_flag = '1' then
2907  bad_l1id_flag <= '1';
2908  else
2909  bad_l1id_flag <= bad_l1id_flag;
2910  end if;
2911  end if;
2912 end process;
2913 --decision needed on event_sel should take any precidence of TTC_ignore. I think even_sel(1) should be ignored here
2914 -- when "100" | "101" =>
2915 -- event_en <= '0';
2916 -- when others =>
2917 -- event_en <= '1';
2918 -- end case;
2919 --end process;
2920 
2925 process (clock) begin
2926  if rising_edge (clock) then
2927  if (reset = '1') or (tob_pkt_active = '1') then
2928  l1id_resync_flag <= '0';
2929  elsif (state = dbg_trlr_ld_last) and (current_chan = num_chan) and (bad_l1id_flag = '1') and (tob_pkt_active = '0') and (l1id_resync_enable = '1') then
2930  l1id_resync_flag <= not l1id_resync_flag;
2931  else
2932  l1id_resync_flag <= l1id_resync_flag;
2933  end if;
2934  end if;
2935 end process;
2936 
2937 
2938 
2939 --top level outputs
2940 -- m_tvalid : out STD_LOGIC;
2941 -- m_tlast : out STD_LOGIC;
2942 -- m_tdata : out STD_LOGIC_VECTOR ((bp_width-1) downto 0);
2943 -- m_header_marker : out STD_LOGIC;
2944 -- m_tail_marker : out STD_LOGIC;
2945 -- m_tready : in STD_LOGIC
2946 
2947 --tob_fifo_outputs
2948 -- m_axis_tvalid => tob_m_tvalid_i,
2949 -- m_axis_tlast => tob_m_tlast_i,
2950 -- m_axis_tready => tob_m_tready,
2951 -- m_axis_tuser(1) => tob_m_header_marker_i,
2952 -- m_axis_tuser(0) => tob_m_tail_marker_i,
2953 -- m_axis_tdata => tob_m_tdata_i,
2954 --
2955 -- axis_data_count => tob_data_count,
2956 -- axis_wr_data_count => tob_wr_data_count,
2957 -- axis_rd_data_count => tob_rd_data_count
2958 
2959 -- debug fifo outputs
2960 
2961 -- m_axis_tvalid => dbg_m_tvalid_i,
2962 -- m_axis_tlast => dbg_m_tlast_i,
2963 -- m_axis_tready => dbg_m_tready,
2964 -- m_axis_tuser(1) => dbg_m_header_marker_i,
2965 -- m_axis_tuser(0) => dbg_m_tail_marker_i,
2966 -- m_axis_tdata => dbg_m_tdata_i,
2967 
2968 -- axis_data_count => open,
2969 -- axis_wr_data_count => open,
2970 -- axis_rd_data_count => open
2971 
2972 
2973 
2974 
2975 
2976 
2977 
2978 State_machine_ILA : ILA_ev_builder
2979 PORT MAP (
2980  clk => clock,
2981  probe0 => state,
2982  probe1 => current_chan,
2983  probe2 => num_chan,
2984  probe3(0) => chan_enable,
2985  probe4(0) => header_fifo_valid,
2986  probe5(0) => timeout_n,
2987  probe6(0) => timeout_1,
2988  probe7(0) => s_header_mark,
2989  probe8(0) => s_hdr_crc_tag,
2990  probe9(0) => s_tvalid,
2991  probe10(0) => s_tlast,
2992  probe11(0) => L1ID_eq,
2993  probe12(0) => L1ID_reg_eq,
2994  probe13(0) => ttc_ignore,
2995  probe14 => L1ID_ttc_hreg,
2996 -- probe15(0) => lead_follow_b_reg,
2997  probe15(0) => crc20_err,
2998  probe16 => chan_len_cnt, -- chan_in,
2999  probe17(0) => pet_timer,
3000  probe18(0) => stop_timeout,
3001  probe19 => timeout_counter,
3002  probe20(0) => timeout_run,
3003  probe21(0) => wdog_overflow_i,
3004  probe22(0) => wdog_pet,
3005  probe23(0) => wdog_disable,
3006  probe24 => wdog_threshold,
3007  probe25 => s_tdata,
3008  probe26(0) => flx_backpressure,
3009  probe27(0) => stop_proc,
3010  probe28 => l1id_measure_time(16 downto 1),
3011  probe29 => l1id_measure_max
3012 
3013 );
3014 
3015 
3016 
3017 wdog_timer : watchdog
3018  generic map ( overflow_clock_count => x"0f"
3019  )
3020  Port map (
3021  pp_clock => clock,
3022  reset_in => reset,
3023  wdog_disable => wdog_disable,
3024  wdog_pet => wdog_pet,
3025  wdog_threshold => wdog_threshold,
3026  wdog_overflow => wdog_overflow_i
3027  );
3028 
3029 
3030 wdog_pet <= '1' when ((current_state = wait_for_event)or (current_state = await_resync)) else '0';
3031 wdog_overflow <= wdog_overflow_i;
3032 
3033 
3034 --------------------------------------------------------------------
3035 --instrumentation to measure time waiting for packet Rx following L1A
3036 -------------------------------------------------------------------
3037 
3038 --look for rising edge of header_fifo_valid -- may be better to use processor state-12 to begin measurement
3039 process (clock) begin
3040  if rising_edge (clock) then
3041  header_fifo_valid_del <= header_fifo_valid;
3042  end if;
3043 end process;
3044 
3045 
3046 --make lock control so that a measurement in progress is not disturbed by a new event
3047 process (clock) begin
3048  if rising_edge (clock) then
3049  if (rx_timer_clear = '1') then
3050  l1id_measure_lock <= '0';
3051  elsif ((header_fifo_valid_del ='0') and (header_fifo_valid = '1') and (l1id_measure_lock = '0')) then
3052  l1id_measure_reg <= master_header(43 downto 12);
3053  l1id_measure_lock <= '1';
3054  else
3055  l1id_measure_reg <= l1id_measure_reg;
3056  l1id_measure_lock <= l1id_measure_lock;
3057  end if;
3058  end if;
3059 end process;
3060 
3061 
3062 --calculate measured packet arrival time for this event - last time
3063 process (clock) begin
3064  if rising_edge (clock) then
3065  if (clr_pkt_wait_timer = '1') then
3066  l1id_measure_last_i <= x"0000_0000";
3067  l1id_measure_time <= x"0000_0000";
3068  elsif (rx_timer_clear = '1') then
3069  l1id_measure_time <= x"0000_0000";
3070  elsif (l1id_measure_lock = '1') then
3071  l1id_measure_time <= (l1id_measure_time + 1);
3072  l1id_measure_last_i <= l1id_measure_time;
3073  else
3074  l1id_measure_time <= l1id_measure_time;
3075  l1id_measure_last_i <= l1id_measure_last_i;
3076  end if;
3077  end if;
3078 end process;
3079 
3080 --calculate max measured packet arrival time
3081 process (clock) begin
3082  if rising_edge (clock) then
3083  if (clr_pkt_wait_timer = '1') then
3084  l1id_measure_max_i <= x"0000_0000";
3085  l1id_max_l1id <= x"0000_0000";
3086  elsif (rx_timer_clear = '1') then
3087  l1id_measure_max_i <= l1id_measure_max_i;
3088  elsif (l1id_measure_max_i < l1id_measure_time) and (l1id_measure_lock = '1') then
3089  l1id_measure_max_i <= l1id_measure_time;
3090  l1id_max_l1id <= l1id_measure_reg;
3091  --l1id_max_chan <= current_chan; --proto for adding a channel register because early channels may have timeed out
3092  else
3093  l1id_measure_max_i <= l1id_measure_max_i;
3094  l1id_max_l1id <= l1id_max_l1id;
3095  --l1id_max_chan <= l1id_max_chan;
3096  end if;
3097  end if;
3098 end process;
3099 
3100 
3101 
3102 
3103 --register the last/max values to be displayed to ipbus. These are shifted right by 1
3104 process (clock) begin
3105  if rising_edge (clock) then
3106  if (clr_pkt_wait_timer = '1') then
3107  l1id_measure_last <= x"0000_0000";
3108  l1id_measure_max <= x"0000_0000";
3109  elsif (rx_timer_clear = '1') and (l1id_measure_lock = '1') then
3110  l1id_measure_last <= '0' & l1id_measure_last_i(31 downto 1);
3111  l1id_measure_max <= '0' & l1id_measure_max_i(31 downto 1);
3112  end if;
3113  end if;
3114 end process;
3115 
3116 --create rx_timer_clear signal
3117 process (clock) begin
3118  if rising_edge (clock) then
3119  if (clr_pkt_wait_timer = '1') or ((s_header_mark = '1') and (s_tdata(63 downto 32) = l1id_measure_reg) and (l1id_measure_lock = '1')) then --and chan = chan_time
3120  rx_timer_clear <= '1';
3121  elsif rx_timer_clear = '1' then
3122  rx_timer_clear <= '0';
3123  else
3124  rx_timer_clear <= rx_timer_clear;
3125  end if;
3126  end if;
3127 end process;
3128 
3129 
3130 
3131 --timeout_counter_max
3132 Process (clock) begin
3133  if rising_edge(clock) then
3134  if (clr_max_timeout = '1') then
3135  timeout_counter_max_i <= x"0000";
3136  elsif (timeout_counter > timeout_counter_max_i) then
3137  timeout_counter_max_i <= timeout_counter;
3138  max_chan_i <= current_chan;
3139  else
3140  timeout_counter_max_i <= timeout_counter_max_i;
3141  max_chan_i <= max_chan_i;
3142  end if;
3143  end if;
3144 end process;
3145 
3146 max_chan <= max_chan_i;
3147 timeout_counter_max <= timeout_counter_max_i;
3148 
3149 ----timeout_counter_last
3150 --Process (clock) begin
3151 -- if rising_edge(clock) then
3152 -- if (clr_max_timeout = '1') then
3153 -- timeout_counter_last_i <= x"0000";
3154 -- elsif ((s_header_mark = '1') and (s_tdata(63 downto 32) = l1id_measure_reg) and (s_tvalid = '1') and (timeout_counter_last_lock = '0')) then
3155 -- timeout_counter_last_i <= timeout_counter;
3156 -- timeout_counter_last_lock <= '1';
3157 -- elsif (s_header_mark = '0') then
3158 -- timeout_counter_last_lock <= '0';
3159 -- else
3160 -- timeout_counter_last_i <= timeout_counter_last_i;
3161 
3162 -- end if;
3163 -- end if;
3164 -- end process;
3165 -- timeout_counter_last <= timeout_counter_last_i;
3166 
3167 
3168 l1id_max_l1id_o <= l1id_max_l1id;
3169 l1id_measure_max_o <= l1id_measure_max;
3170 l1id_measure_last_o <= l1id_measure_last;
3171 -------------------------------------------------end of rx timer -------------------------
3172 --ila_pkt_rx_time : rx_time_ila
3173 --PORT MAP (
3174 -- clk => clock,
3175 -- probe0 => l1id_measure_time,
3176 -- probe1 => l1id_measure_last,
3177 -- probe2 => l1id_measure_max,
3178 -- probe3 => l1id_measure_reg,
3179 -- probe4 => s_tdata(63 downto 32),
3180 -- probe5(0) => s_header_mark,
3181 -- probe6(0) => l1id_measure_lock,
3182 -- probe7(0) => rx_timer_clear
3183 -- );
3184 
3185 
3186 end RTL;
CRC
Definition: crc.vhd:25
controller_codes
Definition: controller_codes.vhd:25
ev_builder.RTL
Definition: ev_builder.vhd:208
ev_builder
Definition: ev_builder.vhd:86
event_hdr_crc9
Definition: event_hdr_crc9.vhd:42
event_trailer_CRC20
Definition: event_trailer_CRC20.vhd:40
ff
Definition: ff.vhd:34
hdr_in_crc9
Definition: hdr_in_crc9.vhd:40
tob_timeout
Definition: tob_timeout.vhd:46
trailer_map
Definition: trailer_map.vhd:34
vDFF
Definition: ff.vhd:57
Generated on Sat Dec 14 2024 13:33:14 for ROD firmware by   doxygen 1.9.1