Processes
PROCESS_285	( ipb_clk )
PROCESS_286	( pp_clock )
PROCESS_287	( rt_clk )
PROCESS_288	( rt_clk , ipb_rst , flx_bp_count_reset )
PROCESS_289	( pp_clock )
PROCESS_290	( pp_clock )
PROCESS_291	( pp_clock )
PROCESS_292	( pp_clock )
PROCESS_293	( pp_clock )

Signals
ipbw	ipb_wbus_array ( N_SLAVES- 1 downto 0 )
ipbr	ipb_rbus_array ( N_SLAVES- 1 downto 0 )
event_fifo_rst_stb	std_logic
event_fifo_rst_rst	std_logic
event_fifo_control	std_logic_vector ( 31 downto 0 )
event_fifo_reset	std_logic_vector ( 31 downto 0 )
event_fifo_fill_level	std_logic_vector ( 31 downto 0 )
event_watermark_reset	std_logic
event_watermark	std_logic_vector ( 15 downto 0 )
debug_fifo_rst_stb	std_logic
debug_fifo_rst_rst	std_logic
debug_fifo_control	std_logic_vector ( 31 downto 0 )
debug_fifo_reset	std_logic_vector ( 31 downto 0 )
debug_fifo_fill_level	std_logic_vector ( 31 downto 0 )
debug_watermark_reset	std_logic
debug_watermark	std_logic_vector ( 15 downto 0 )
stage_watermark	std_logic_vector ( 15 downto 0 )
stage_watermark_reset	std_logic
stage_fifo_fill_level	std_logic_vector ( 31 downto 0 )
fm_watermark	std_logic_vector ( 15 downto 0 )
fm_watermark_reset	std_logic
fm_fifo_fill_level	std_logic_vector ( 31 downto 0 )
fm_L1id_i	std_logic_vector ( 31 downto 0 )
full_mode_stat_i	std_logic_vector ( 31 downto 0 )
fm_fifo_level	std_logic_vector ( 15 downto 0 )
processor_status	std_logic_vector ( 31 downto 0 )
staging_threshold	std_logic_vector ( 31 downto 0 )
tob_stage_busy_thresh	std_logic_vector ( 15 downto 0 )
tob_stage_xoff_thresh	std_logic_vector ( 15 downto 0 )
staging_control	std_logic_vector ( 31 downto 0 )
busy_enable	std_logic
xoff_enable	std_logic
force_busy	std_logic
stage_fifo_rst_stb	std_logic
stage_fifo_rst_rst	std_logic
stage_fifo_reset_bits	std_logic_vector ( 31 downto 0 )
stage_busy_thresh_reset	std_logic
stage_xoff_thresh_reset	std_logic
stage_fifo_reset	std_logic
full_mode_stat_reset	std_logic
Stage_fifo_busy_Count	std_logic_vector ( 31 downto 0 )
Stage_fifo_xoff_Count	std_logic_vector ( 31 downto 0 )
stage_fifo_busy_i	std_logic
stage_fifo_xoff_i	std_logic
stage_fifo_status	std_logic_vector ( 31 downto 0 )
load_init_value	std_logic
timeout_defaults	std_logic_vector ( 31 downto 0 )
tob_timeouts	std_logic_vector ( 31 downto 0 )
crc20_cnt	std_logic_vector ( 7 downto 0 )
crc9_cnt	std_logic_vector ( 7 downto 0 )
bcn_cnt	std_logic_vector ( 7 downto 0 )
bad_l1id_cnt	std_logic_vector ( 7 downto 0 )
clr_crc20_cnt	std_logic
clr_crc9_cnt	std_logic
clr_bcn_cnt	std_logic
clr_l1id_cnt	std_logic
clr_wdog_cnt	std_logic
clr_timeout_err	std_logic
tob_proc_rst_rst	std_logic
tob_proc_rst_stb	std_logic
tob_proc_reg_reset	std_logic_vector ( 31 downto 0 )
load_defaults	std_logic
watchdog_default	std_logic_vector ( 31 downto 0 )
wdog_threshold_i	std_logic_vector ( 31 downto 0 )
watchdog_control	std_logic_vector ( 31 downto 0 )
wdog_overflow_count	std_logic_vector ( 31 downto 0 )
wdog_fifo_reset_en	std_logic
crc9_map	std_logic_vector ( 23 downto 0 )
crc20_map	std_logic_vector ( 23 downto 0 )
bcn_map	std_logic_vector ( 23 downto 0 )
l1id_map	std_logic_vector ( 23 downto 0 )
timeout_map	std_logic_vector ( 23 downto 0 )
clr_crc9_cnt_s	std_logic
clr_crc20_cnt_s	std_logic
clr_BCN_cnt_s	std_logic
clr_l1id_cnt_s	std_logic
clr_timeout_s	std_logic
clr_event_timer	std_logic
event_time	std_logic_vector ( 15 downto 0 )
max_event_time	std_logic_vector ( 15 downto 0 )
avg_event_time	std_logic_vector ( 15 downto 0 )
trace_input	std_logic_vector ( 23 downto 0 )
full_mode_ctrl_i	std_logic_vector ( 31 downto 0 )
flx_bp_count_reset	std_logic
flx_bp_enable	std_logic
flx_bp_time	std_logic_vector ( 31 downto 0 )
idle_status	std_logic
L1ID	std_logic_vector ( 23 downto 0 )
ECRID	std_logic_vector ( 7 downto 0 )
l1id_ttc	std_logic_vector ( 31 downto 0 )
stage_fifo_xoff_sync	std_logic
stage_fifo_busy_sync	std_logic
xoff_condition	std_logic
busy_condition	std_logic
flx_backpressure_raw	std_logic
flx_backpressure_rt	std_logic
max_timeout_and_chan	std_logic_vector ( 31 downto 0 )
current_chan	STD_LOGIC_VECTOR ( 7 downto 0 )
chan_count	STD_LOGIC_VECTOR ( 4 downto 0 )

Instantiations
fabric	ipbus_fabric_sel
event_fifo_control_reg	ipbus_reg_v
event_fifo_reset_reg	ipbus_reg_v
event_fifo_fill_level_reg	ipbus_syncreg_v
event_fifo_watermark	watermark <Entity watermark>
debug_fifo_fill_level_reg	ipbus_syncreg_v
debug_fifo_watermark	watermark <Entity watermark>
tob_proc_status	ipbus_syncreg_v
full_mode_control_reg	ipbus_reg_v
full_mode_status_reg	ipbus_syncreg_v
stage_fifo_fill_level_reg	ipbus_syncreg_v
stage_fifo_watermark	watermark <Entity watermark>
fullmode_fifo_fill_level_reg	ipbus_syncreg_v
fm_fifo_watermark	watermark <Entity watermark>
fm_l1id_reg	ipbus_syncreg_v
tob_staging_thresholds_reg	ipbus_reg_v
tob_staging_control_reg	ipbus_reg_v
tob_staging_fifo_resets_reg	ipbus_reg_v
tob_stage_fifo_status_reg	ipbus_syncreg_v
tob_stage_busy_count_reg	ipbus_syncreg_v
tob_stage_xoff_count_reg	ipbus_syncreg_v
tob_timeout_reg	ipbus_ctrlreg_v
error_count_register	ipbus_syncreg_v
tob_proc_reset_reg	ipbus_reg_v
packet_capture	pkt_capture_regs <Entity pkt_capture_regs>
input_capture	input_capture_regs <Entity input_capture_regs>
watchdog_control_reg	ipbus_reg_v
wdog_threshold_reg	ipbus_ctrlreg_v
watchdog_overflow_count_reg	ipbus_syncreg_v
wdog_overflow_counter	edge_error_counter <Entity edge_error_counter>
crc9_error_map_reg	ipbus_syncreg_v
crc20_error_map_reg	ipbus_syncreg_v
bcn_mismatch_map_reg	ipbus_syncreg_v
l1id_mismatch_map_reg	ipbus_syncreg_v
timeout_error_map_reg	ipbus_syncreg_v
chan_error_mapper	chan_err_map <Entity chan_err_map>
avg_event_time_reg	ipbus_syncreg_v
event_time_reg	ipbus_syncreg_v
dbg_pkt_count_reg	ipbus_syncreg_v
flx_bp_time_reg	ipbus_syncreg_v
pkt_wait_time_last_reg	ipbus_syncreg_v
pkt_wait_time_max_reg	ipbus_syncreg_v
pkt_max_wait_time_l1id_reg	ipbus_syncreg_v
max_timeout_reg	ipbus_syncreg_v
event_proc_timer	event_timer <Entity event_timer>
trace_module	Processor_trace_module <Entity Processor_trace_module>
l1id_capt	l1id_capture <Entity l1id_capture>
tob_stage_busy_counter	threshold_counter <Entity threshold_counter>
tob_stage_busy_flag	threshold_counter <Entity threshold_counter>
tob_stage_xoff_counter	threshold_counter <Entity threshold_counter>
tob_stage_xoff_flag	threshold_counter <Entity threshold_counter>

Detailed Description

Definition at line 124 of file tob_proc_regs.vhd.

The documentation for this class was generated from the following file:

ROD/packet_processor/hdl/tob_proc_regs.vhd

Components
pkt_capture_regs	<Entity pkt_capture_regs>
l1id_capture	<Entity l1id_capture>
input_capture_regs	<Entity input_capture_regs>
Processor_trace_module	<Entity Processor_trace_module>
edge_error_counter	<Entity edge_error_counter>
chan_err_map	<Entity chan_err_map>
default_reg_ila
event_timer	<Entity event_timer>

Processes

Components

Signals

Instantiations

Detailed Description