ROD firmware  1.0.5
ATLAS l1-calo - ROD_eFEX and ROD_jFEX firmware for the L1Calo ROD board

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tob_proc_regs.vhd
1 ----------------------------------------------------------------------------------
2 -- Company:
3 -- Engineer:
4 --
5 -- Create Date: 05.02.2020 10:08:23
6 -- Design Name:
7 -- Module Name: tob_proc_regs - RTL
8 -- Project Name:
9 -- Target Devices:
10 -- Tool Versions:
11 -- Description:
12 --
13 -- Dependencies:
14 --
15 -- Revision:
16 -- Revision 0.01 - File Created
17 -- Additional Comments:
18 --
19 ----------------------------------------------------------------------------------
20 
21 
22 library IEEE;
23 use IEEE.STD_LOGIC_1164.ALL;
24 use IEEE.NUMERIC_STD.ALL;
25 use IEEE.STD_LOGIC_UNSIGNED.ALL;
26 use work.ipbus.all;
27 use work.ipbus_decode_L1CaloHubRodTobProc.all;
28 -- Uncomment the following library declaration if using
29 -- arithmetic functions with Signed or Unsigned values
30 --use IEEE.NUMERIC_STD.ALL;
31 
32 -- Uncomment the following library declaration if instantiating
33 -- any Xilinx leaf cells in this code.
34 --library UNISIM;
35 --use UNISIM.VComponents.all;
36 
37 entity tob_proc_regs is
38  generic (
39  sim : integer := 0;
40  timeout_1_default : std_logic_vector(15 downto 0) := x"0600";
41  timeout_n_default : std_logic_vector(15 downto 0) := x"0030";
42  wdog_thresh_default : std_logic_vector(15 downto 0) := x"2000"
43  );
44  port(
45  ipb_clk : in std_logic;
46  ipb_rst : in std_logic;
47  ipb_in : in ipb_wbus;
48  ipb_out : out ipb_rbus;
49 
50  pp_clock : in std_logic;
51  rt_clk : in std_logic;
52  reset : in std_logic;
53  event_fifo_level : in STD_LOGIC_VECTOR (15 downto 0); --synchronous to the pp_clock
54  debug_fifo_level : in STD_LOGIC_VECTOR (15 downto 0); --synchronous to the pp_clock
55  stage_fifo_level : in std_logic_vector (15 downto 0);
56 -- current_chan : in STD_LOGIC_VECTOR (7 downto 0);
57  first_chan : in STD_LOGIC_vector (4 downto 0);
58  current_state : in STD_LOGIC_VECTOR (7 downto 0);
59  header_mark : in std_logic;
60  header_fifo_valid : in std_logic;
61  hdr_crc_error : in std_logic;
62  ttc_crc_error : in std_logic;
63  crc20_err : in STD_LOGIC; --1 cycle pulse: used for counting
64  crc9_err : in STD_LOGIC; --1 cycle pulse: used for counting
65  BCID_mismatch : in STD_LOGIC; --1 cycle pulse: used for counting
66  L1ID_mismatch : in STD_LOGIC; --1 cycle pulse: used for counting
67  timeout_err : in STD_LOGIC; --1 cycle pulse: no counter implemented
68  crc20_err_chan : in STD_LOGIC_VECTOR (4 downto 0);
69 
70  --output capture regs
71  full_mode_ctrl : out STD_LOGIC_VECTOR (31 downto 0);
72  full_mode_stat : in STD_LOGIC_VECTOR (31 downto 0);
73  FM_L1id_stat : in std_logic_vector (31 downto 0);
74  m_tdata : in STD_LOGIC_VECTOR (63 downto 0);
75  m_tvalid : in std_logic;
76  m_tlast : in std_logic;
77  m_header_marker : in std_logic;
78 -- master_header : in STD_LOGIC_VECTOR (63 downto 0);
79  L1ID_ttc_32_reg : in STD_LOGIC_VECTOR (31 downto 0);
80 
81  s_tdata : in STD_LOGIC_VECTOR (63 downto 0);
82  s_tvalid : in std_logic;
83  s_tlast : in std_logic;
84  s_header_mark : in std_logic;
85  poll_chan : in std_logic;
86 
87  stage_fifo_busy : out STD_LOGIC;
88  stage_fifo_xoff : out STD_LOGIC;
89  stage_fifo_full : in STD_LOGIC;
90  timeout_1_val : out STD_LOGIC_VECTOR (15 downto 0);
91  timeout_n_val : out STD_LOGIC_VECTOR (15 downto 0);
92 
93  wdog_overflow : in STD_LOGIC;
94  wdog_threshold : out STD_LOGIC_VECTOR (15 downto 0);
95  wdog_disable : out STD_LOGIC;
96  wdog_fifo_reset : out STD_LOGIC;
97  l1id_resync_enable: out STD_LOGIC;
98 
99  tob_timeout_1_disable : out STD_LOGIC;
100  tob_timeout_n_disable : out STD_LOGIC;
101 
102  dbg_pkt_count : in STD_LOGIC_VECTOR (31 downto 0);
103  dbg_pkt_count_reset : out STD_LOGIC;
104  flx_backpressure : in STD_LOGIC_vector(11 downto 0);
105  flx_backpressure_bit : out STD_LOGIC;
106  stop_proc : out STD_LOGIC;
107 
108  l1id_max_l1id : in std_logic_VECTOR (31 downto 0);
109  l1id_measure_max : in std_logic_VECTOR (31 downto 0);
110  l1id_measure_last : in std_logic_VECTOR (31 downto 0);
111  clr_pkt_wait_timer : out STD_LOGIC;
112  timeout_counter_max : in std_logic_VECTOR (15 downto 0);
113  max_chan : in std_logic_VECTOR (4 downto 0);
114  clr_max_timeout : out STD_LOGIC;
115 
116 ---signals for local "current chan"
117  last_chan : in STD_LOGIC_vector (4 downto 0);
118  nxt_chan_0 : in STD_LOGIC;
119  chan_pointer_reset : in STD_LOGIC
120 
121  );
122 end tob_proc_regs;
123 
124 architecture RTL of tob_proc_regs is
125 
126 component pkt_capture_regs is
127  generic (
128  sim : integer := 0;
129  debug : integer := 1
130  );
131  Port (
132 
133  ipb_clk : in std_logic;
134  ipb_rst : in std_logic;
135  ipb_in : in ipb_wbus;
136  ipb_out : out ipb_rbus;
137  pp_clock : in std_logic;
138 -- full_mode_ctrl : out STD_LOGIC_VECTOR (31 downto 0);
139  full_mode_stat : in STD_LOGIC_VECTOR (31 downto 0);
140  m_tdata : in STD_LOGIC_VECTOR (63 downto 0);
141  m_tvalid : in std_logic;
142  m_tlast : in std_logic;
143  m_header_marker : in std_logic
144 
145  );
146 end component;
147 
148 component l1id_capture
149  generic (
150  sim : integer := 0
151  );
152  Port (
153  ipb_clk : in std_logic;
154  ipb_rst : in std_logic;
155  ipb_in : in ipb_wbus;
156  ipb_out : out ipb_rbus;
157  pp_clock : in STD_LOGIC;
158  reset : in STD_LOGIC;
159  s_tvalid : in STD_LOGIC;
160  s_tlast : in STD_LOGIC;
161  idle_state : in STD_LOGIC;
162  l1id_ttc : in STD_LOGIC_VECTOR(31 downto 0);
163  l1id_pkt : in STD_LOGIC_VECTOR(31 downto 0);
164  current_chan : in STD_LOGIC_VECTOR(7 downto 0); --allow any channel to mismatch, and then record that channel
165  first_chan : in STD_LOGIC_vector (4 downto 0); --only capture the new ttc_l1id on the first chnnel
166  poll_chan : in STD_LOGIC
167  );
168 end component;
169 
170 
171 component input_capture_regs is
172  generic (
173  sim : integer := 0;
174  debug : integer := 1
175  );
176  Port (
177 
178  ipb_clk : in std_logic;
179  ipb_rst : in std_logic;
180  ipb_in : in ipb_wbus;
181  ipb_out : out ipb_rbus;
182  pp_clock : in std_logic;
183  current_chan : in STD_LOGIC_VECTOR (4 downto 0);
184  s_tdata : in STD_LOGIC_VECTOR (63 downto 0);
185  s_tvalid : in std_logic;
186  s_tlast : in std_logic;
187  s_header_mark : in std_logic;
188  poll_chan : in std_logic;
189  timeout_err : in std_logic
190 
191  );
192 end component;
193 
194 
195 component Processor_trace_module is
196  generic(
197  ADDR_WIDTH: positive := 8;
198  DATA_WIDTH: positive := 32
199  );
200  Port (
201  ipb_clk : in std_logic;
202  ipb_rst : in std_logic;
203  ipb_in : in ipb_wbus;
204  ipb_out : out ipb_rbus;
205 
206  pp_clock : in STD_LOGIC;
207  reset : in STD_LOGIC;
208  trace_input : in STD_LOGIC_VECTOR (23 downto 0); --connect to signals to be traced in addition to state
209  state : in STD_LOGIC_VECTOR (7 downto 0); --processor "state" plus any other signals to trace
210  wd_event : in STD_LOGIC; --watchdog overflow signal
211  timeout_error : in STD_LOGIC --one pp_clock cycle timeout error pulse
212 
213 );
214 
215 end component;
216 
217 component edge_error_counter
218  generic(
219  cwidth: positive := 4
220  );
221  Port (
222  clock : in STD_LOGIC;
223  counter_reset : in STD_LOGIC;
224  system_reset : in STD_LOGIC;
225  error : in STD_LOGIC;
226  error_count : out STD_LOGIC_VECTOR(cwidth-1 downto 0)
227 
228  );
229 end component;
230 
231 component chan_err_map
232  generic (
233  jfex : integer := 1
234  );
235  Port (
236  clock : in std_logic;
237  reset_0 : in std_logic;
238  reset_1 : in std_logic;
239  reset_2 : in std_logic;
240  reset_3 : in std_logic;
241  reset_4 : in std_logic;
242  error_0 : in std_logic;
243  error_1 : in std_logic;
244  error_2 : in std_logic;
245  error_3 : in std_logic;
246  error_4 : in std_logic;
247  sample_0 : in std_logic;
248  sample_1 : in std_logic;
249  sample_2 : in std_logic;
250  sample_3 : in std_logic;
251  sample_4 : in std_logic;
252  chan_in : in STD_LOGIC_VECTOR (4 downto 0);
253  error_map_0 : out STD_LOGIC_VECTOR (23 downto 0);
254  error_map_1 : out STD_LOGIC_VECTOR (23 downto 0);
255  error_map_2 : out STD_LOGIC_VECTOR (23 downto 0);
256  error_map_3 : out STD_LOGIC_VECTOR (23 downto 0);
257  error_map_4 : out STD_LOGIC_VECTOR (23 downto 0)
258  );
259 end component;
260 
261 COMPONENT default_reg_ila
262 
263 PORT (
264  clk : IN STD_LOGIC;
265  probe0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
266  probe1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
267  probe2 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
268  probe3 : IN STD_LOGIC_VECTOR(0 DOWNTO 0)--;
269 -- probe4 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
270 -- probe5 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
271 -- probe6 : IN STD_LOGIC_VECTOR(0 DOWNTO 0)
272 );
273 END COMPONENT ;
274 
275 component event_timer is
276  generic ( start_state : std_logic_vector := x"02"; --start_reading
277  stop_state : std_logic_vector := x"11" --wait for event
278  );
279 
280  Port ( clock : in STD_LOGIC; --processor clock
281  reset : in STD_LOGIC; --reset from a pulse register or reset
282  current_state : in STD_LOGIC_vector (7 downto 0); --current_state of the processor
283 
284 
285  event_time : out std_logic_vector(15 downto 0) ; --duration of last event processing - route to ipbus register
286  watermark : out std_logic_vector(15 downto 0); --largest duration recorded - route to ipbus register
287  avg_time : out std_logic_vector(15 downto 0) --average duration of event processing - route to ipbus register
288  --total 30 bits can be connected to a single read-only register
289 
290  );
291 end component;
292 
293 
294 
295 
296  signal ipbw: ipb_wbus_array(N_SLAVES - 1 downto 0);
297  signal ipbr: ipb_rbus_array(N_SLAVES - 1 downto 0);
298 
299  signal event_fifo_rst_stb : std_logic;
300  signal event_fifo_rst_rst : std_logic;
301  SIGNAL event_fifo_control : std_logic_vector (31 downto 0);
302  signal event_fifo_reset : std_logic_vector (31 downto 0);
303  signal event_fifo_fill_level : std_logic_vector (31 downto 0);
304  signal event_watermark_reset : std_logic;
305  signal event_watermark : std_logic_vector (15 downto 0);
306 
307  signal debug_fifo_rst_stb : std_logic;
308  signal debug_fifo_rst_rst : std_logic;
309  SIGNAL debug_fifo_control : std_logic_vector (31 downto 0);
310  signal debug_fifo_reset : std_logic_vector (31 downto 0);
311  signal debug_fifo_fill_level : std_logic_vector (31 downto 0);
312  signal debug_watermark_reset : std_logic;
313  signal debug_watermark : std_logic_vector (15 downto 0);
314 
315  signal stage_watermark : std_logic_vector (15 downto 0);
316  signal stage_watermark_reset : std_logic;
317  signal stage_fifo_fill_level : std_logic_vector (31 downto 0);
318 
319  signal fm_watermark : std_logic_vector (15 downto 0);
320  signal fm_watermark_reset : std_logic;
321  signal fm_fifo_fill_level : std_logic_vector (31 downto 0);
322  signal fm_L1id_i : std_logic_vector (31 downto 0);
323  signal full_mode_stat_i : std_logic_vector (31 downto 0);
324  signal fm_fifo_level : std_logic_vector (15 downto 0);
325  signal processor_status : std_logic_vector(31 downto 0);
326 
327  signal staging_threshold : std_logic_vector(31 downto 0);
328  signal tob_stage_busy_thresh : std_logic_vector(15 downto 0);
329  signal tob_stage_xoff_thresh : std_logic_vector(15 downto 0);
330 
331  signal staging_control : std_logic_vector(31 downto 0);
332  signal busy_enable : std_logic;
333  signal xoff_enable : std_logic;
334  signal force_busy : std_logic;
335 
336  signal stage_fifo_rst_stb : std_logic;
337  signal stage_fifo_rst_rst : std_logic;
338  signal stage_fifo_reset_bits : std_logic_vector(31 downto 0);
339  signal stage_busy_thresh_reset : std_logic;
340  signal stage_xoff_thresh_reset : std_logic;
341  signal stage_fifo_reset : std_logic;
342  signal full_mode_stat_reset : std_logic;
343 
344  signal Stage_fifo_busy_Count : std_logic_vector(31 downto 0);
345  signal Stage_fifo_xoff_Count : std_logic_vector(31 downto 0);
346  signal stage_fifo_busy_i : std_logic;
347  signal stage_fifo_xoff_i : std_logic;
348  signal stage_fifo_status : std_logic_vector(31 downto 0);
349  signal load_init_value : std_logic;
350  signal timeout_defaults : std_logic_vector(31 downto 0);
351  signal tob_timeouts : std_logic_vector(31 downto 0);
352 
353  signal crc20_cnt : std_logic_vector(7 downto 0);
354  signal crc9_cnt : std_logic_vector(7 downto 0);
355  signal bcn_cnt : std_logic_vector(7 downto 0);
356  signal bad_l1id_cnt : std_logic_vector(7 downto 0);
357  signal clr_crc20_cnt : std_logic;
358  signal clr_crc9_cnt : std_logic;
359  signal clr_bcn_cnt : std_logic;
360  signal clr_l1id_cnt : std_logic;
361  signal clr_wdog_cnt : std_logic;
362  signal clr_timeout_err : std_logic;
363  signal tob_proc_rst_rst : std_logic;
364  signal tob_proc_rst_stb : std_logic;
365  signal tob_proc_reg_reset : std_logic_vector(31 downto 0);
366 
367  signal load_defaults : std_logic;
368 
369  signal watchdog_default : std_logic_vector(31 downto 0);
370  signal wdog_threshold_i : std_logic_vector(31 downto 0);
371  signal watchdog_control : std_logic_vector(31 downto 0);
372  signal wdog_overflow_count : std_logic_vector(31 downto 0);
373  signal wdog_fifo_reset_en : std_logic;
374 
375  signal crc9_map : std_logic_vector(23 downto 0);
376  signal crc20_map : std_logic_vector(23 downto 0);
377  signal bcn_map : std_logic_vector(23 downto 0);
378  signal l1id_map : std_logic_vector(23 downto 0);
379  signal timeout_map : std_logic_vector(23 downto 0);
380 
381  signal clr_crc9_cnt_s : std_logic;
382  signal clr_crc20_cnt_s : std_logic;
383  signal clr_BCN_cnt_s : std_logic;
384  signal clr_l1id_cnt_s : std_logic;
385  signal clr_timeout_s : std_logic;
386 
387  signal clr_event_timer : std_logic;
388  signal event_time : std_logic_vector(15 downto 0) ; --duration of last event processing - route to ipbus register
389  signal max_event_time : std_logic_vector(15 downto 0); --largest duration recorded - route to ipbus register
390  signal avg_event_time : std_logic_vector(15 downto 0);
391 
392  signal trace_input : std_logic_vector(23 downto 0);
393  signal full_mode_ctrl_i : std_logic_vector(31 downto 0);
394 
395  signal flx_bp_count_reset : std_logic;
396  signal flx_bp_enable : std_logic;
397  signal flx_bp_time : std_logic_vector(31 downto 0);
398 
399  signal idle_status : std_logic;
400  signal L1ID : std_logic_vector(23 downto 0);-- <= master_header(35 downto 12);
401  signal ECRID : std_logic_vector(7 downto 0);--<= master_header(43 downto 36);
402  signal l1id_ttc : std_logic_vector(31 downto 0);-- <= (ECRID & L1ID);
403 
404  signal stage_fifo_xoff_sync : std_logic;
405  signal stage_fifo_busy_sync : std_logic;
406  signal xoff_condition : std_logic;
407  signal busy_condition : std_logic;
408  signal flx_backpressure_raw : std_logic;
409  signal flx_backpressure_rt : std_logic;
410  signal max_timeout_and_chan : std_logic_vector(31 downto 0);
411 
412  signal current_chan : STD_LOGIC_VECTOR (7 downto 0);
413  signal chan_count : STD_LOGIC_VECTOR (4 downto 0);
414 
415 begin
416 
417  fabric: entity work.ipbus_fabric_sel
418  generic map(
419  NSLV => N_SLAVES,
420  SEL_WIDTH => IPBUS_SEL_WIDTH)
421  port map(
422  ipb_in => ipb_in,
423  ipb_out => ipb_out,
424  sel => ipbus_sel_L1CaloHubRodTobProc(ipb_in.ipb_addr),
425  ipb_to_slaves => ipbw,
426  ipb_from_slaves => ipbr
427  );
428 ---------------------------------------------------
429 no_sim_regs: if SIM=0 generate
430 -----------------------------------------------------
431 Event_fifo_control_reg: entity work.ipbus_reg_v
432  port map(
433  clk => ipb_clk,
434  reset => ipb_rst,
435  ipbus_in => ipbw(N_SLV_event_fifo_control),
436  ipbus_out => ipbr(N_SLV_event_fifo_control),
437  q(0) => event_fifo_control
438  );
439 
440 Event_fifo_reset_reg: entity work.ipbus_reg_v
441  port map(
442  clk => ipb_clk,
443  reset => event_fifo_rst_rst,
444  ipbus_in => ipbw(N_SLV_event_fifo_reset),
445  ipbus_out => ipbr(N_SLV_event_fifo_reset),
446  stb(0) => event_fifo_rst_stb,
447  q(0) => event_fifo_reset
448  );
449 event_fifo_rst_rst <= event_fifo_rst_stb or ipb_rst;
450 
451 
452 event_fifo_fill_level_reg : entity work.ipbus_syncreg_v
453  generic map (
454  N_CTRL => 0,
455  N_STAT => 1
456  )
457  port map (
458  clk => ipb_clk,
459  rst => ipb_rst,
460  ipb_in => ipbw(N_SLV_Event_fifo_fill_level),
461  ipb_out => ipbr(N_SLV_Event_fifo_fill_level),
462  slv_clk => pp_clock,
463  d(0) => event_fifo_fill_level,
464  qmask => (others => (others => '1')),
465  stb => open,
466  rstb => open
467  );
468 
469 event_fifo_fill_level(15 downto 0) <= event_fifo_level;
470 event_fifo_fill_level(31 downto 16) <= event_watermark;
471 
472 
473 event_fifo_watermark : entity work.watermark
474  generic map (
475  watermark_width => 16
476  )
477  port map (
478  clock => pp_clock,
479  level => event_fifo_level,
480  reset => event_watermark_reset,
481  watermark => event_watermark
482  );
483 
484 event_watermark_reset <= (ipb_rst or event_fifo_reset(1));
485 
486 
487 
488 debug_fifo_fill_level_reg : entity work.ipbus_syncreg_v
489  generic map (
490  N_CTRL => 0,
491  N_STAT => 1
492  )
493  port map (
494  clk => ipb_clk,
495  rst => ipb_rst,
496  ipb_in => ipbw(N_SLV_Debug_fifo_fill_level),
497  ipb_out => ipbr(N_SLV_Debug_fifo_fill_level),
498  slv_clk => pp_clock,
499  d(0) => debug_fifo_fill_level,
500  qmask => (others => (others => '1')),
501  stb => open,
502  rstb => open
503  );
504 
505 debug_fifo_fill_level(15 downto 0) <= debug_fifo_level;
506 debug_fifo_fill_level(31 downto 16) <= debug_watermark;
507 
508 
509 debug_fifo_watermark : entity work.watermark
510  generic map (
511  watermark_width => 16
512  )
513  port map (
514  clock => pp_clock,
515  level => debug_fifo_level,
516  reset => debug_watermark_reset,
517  watermark => debug_watermark
518  );
519 
520 debug_watermark_reset <= (ipb_rst or event_fifo_reset(5));
521 
522 
523 tob_proc_status : entity work.ipbus_syncreg_v
524  generic map (
525  N_CTRL => 0,
526  N_STAT => 1
527  )
528  port map (
529  clk => ipb_clk,
530  rst => ipb_rst,
531  ipb_in => ipbw(N_SLV_Tob_Proc_Status),
532  ipb_out => ipbr(N_SLV_Tob_Proc_status),
533  slv_clk => pp_clock,
534  d(0) => processor_status,
535  qmask => (others => (others => '1')),
536  stb => open,
537  rstb => open
538  );
539 
540 processor_status(7 downto 0) <= current_chan;
541 processor_status(15 downto 8) <= current_state;
542 processor_status(16) <= header_mark;
543 processor_status(17) <= header_fifo_valid;
544 processor_status(18) <= hdr_crc_error;
545 processor_status(19) <= ttc_crc_error;
546 processor_status(31 downto 20) <= (others => '0');
547 
548 
549 Full_mode_control_reg: entity work.ipbus_reg_v
550  port map(
551  clk => ipb_clk,
552  reset => ipb_rst,
553  ipbus_in => ipbw(N_SLV_FULL_MODE_CONTROL),
554  ipbus_out => ipbr(N_SLV_FULL_MODE_CONTROL),
555  q(0) => full_mode_ctrl_i
556  );
557 full_mode_ctrl <= full_mode_ctrl_i;
558 
559 full_mode_status_reg : entity work.ipbus_syncreg_v
560  generic map (
561  N_CTRL => 0,
562  N_STAT => 1
563  )
564  port map (
565  clk => ipb_clk,
566  rst => full_mode_stat_reset,
567  ipb_in => ipbw(N_SLV_FULL_MODE_STATUS),
568  ipb_out => ipbr(N_SLV_FULL_MODE_STATUS),
569  slv_clk => pp_clock,
570  d(0) => full_mode_stat_i,
571  qmask => (others => (others => '1')),
572  stb => open,
573  rstb => open
574  );
575 
576 --full_mode_stat_i <= FM_L1id_stat(31 downto 24) & x"0000" & full_mode_stat(7 downto 0);
577 full_mode_stat_i <= full_mode_stat(31 downto 24) & full_mode_stat(23 downto 16) & x"00" & full_mode_stat(7 downto 0);
578  --packet count --fifo fill level locked & done
579 full_mode_stat_reset <= ipb_rst or event_fifo_reset(9);
580 
581 stage_fifo_fill_level_reg : entity work.ipbus_syncreg_v
582  generic map (
583  N_CTRL => 0,
584  N_STAT => 1
585  )
586  port map (
587  clk => ipb_clk,
588  rst => ipb_rst,
589  ipb_in => ipbw(N_SLV_TOB_Staging_fifo_level),
590  ipb_out => ipbr(N_SLV_TOB_Staging_fifo_level),
591  slv_clk => pp_clock,
592  d(0) => stage_fifo_fill_level,
593  qmask => (others => (others => '1')),
594  stb => open,
595  rstb => open
596  );
597 
598 stage_fifo_fill_level(15 downto 0) <= stage_fifo_level;
599 stage_fifo_fill_level(31 downto 16) <= stage_watermark;
600 
601 
602 stage_fifo_watermark : entity work.watermark
603  generic map (
604  watermark_width => 16
605  )
606  port map (
607  clock => pp_clock,
608  level => stage_fifo_level,
609  reset => stage_watermark_reset,
610  watermark => stage_watermark
611  );
612 
613 --stage_watermark_reset <= (ipb_rst or event_fifo_reset(4));
614 
615 
616 fullmode_fifo_fill_level_reg : entity work.ipbus_syncreg_v
617  generic map (
618  N_CTRL => 0,
619  N_STAT => 1
620  )
621  port map (
622  clk => ipb_clk,
623  rst => ipb_rst,
624  ipb_in => ipbw(N_SLV_FULL_MODE_FIFO_LEVEL),
625  ipb_out => ipbr(N_SLV_FULL_MODE_FIFO_LEVEL),
626  slv_clk => pp_clock,
627  d(0) => fm_fifo_fill_level,
628  qmask => (others => (others => '1')),
629  stb => open,
630  rstb => open
631  );
632 
633 fm_fifo_fill_level(15 downto 0) <= fm_fifo_level(15 downto 0);
634 fm_fifo_fill_level(31 downto 16) <= fm_watermark;
635 
636 
637 fm_fifo_level(15 downto 0) <= x"00" & full_mode_stat(23 downto 16);
638 
639 
640 
641 
642 
643 
644 
645 
646 fm_fifo_watermark : entity work.watermark
647  generic map (
648  watermark_width => 16
649  )
650  port map (
651  clock => pp_clock,
652  level => fm_fifo_level,
653  reset => fm_watermark_reset,
654  watermark => fm_watermark
655  );
656 
657 fm_watermark_reset <= (ipb_rst or event_fifo_reset(8));
658 
659 
660 
661 
662 
663 
664 
665 
666 
667 
668 fm_L1id_reg : entity work.ipbus_syncreg_v
669  generic map (
670  N_CTRL => 0,
671  N_STAT => 1
672  )
673  port map (
674  clk => ipb_clk,
675  rst => ipb_rst,
676  ipb_in => ipbw(N_SLV_FULL_MODE_L1ID),
677  ipb_out => ipbr(N_SLV_FULL_MODE_L1ID),
678  slv_clk => pp_clock,
679  d(0) => fm_L1id_i,
680  qmask => (others => (others => '1')),
681  stb => open,
682  rstb => open
683  );
684 
685 --fm_L1id_i <= x"00" & FM_L1id_stat(23 downto 0);
686 fm_L1id_i <= FM_L1id_stat(31 downto 0);
687 
688 --Tob_staging_fifo_thresholds
689 
690 tob_staging_thresholds_reg: entity work.ipbus_reg_v
691  port map(
692  clk => ipb_clk,
693  reset => ipb_rst,
694  ipbus_in => ipbw(N_SLV_Tob_staging_fifo_thresholds),
695  ipbus_out => ipbr(N_SLV_Tob_staging_fifo_thresholds),
696  q(0) => staging_threshold
697  );
698 
699 tob_stage_busy_thresh <= staging_threshold(15 downto 0);
700 tob_stage_xoff_thresh <= staging_threshold(31 downto 16);
701 
702 --Tob_staging_fifo_control
703 
704 tob_staging_control_reg: entity work.ipbus_reg_v
705  port map(
706  clk => ipb_clk,
707  reset => ipb_rst,
708  ipbus_in => ipbw(N_SLV_Tob_staging_fifo_control),
709  ipbus_out => ipbr(N_SLV_Tob_staging_fifo_control),
710  q(0) => staging_control
711  );
712 busy_enable <= staging_control(0);
713 xoff_enable <= staging_control(1);
714 force_busy <= staging_control(4);
715 
716 --Tob_staging_fifo_resets
717 
718 Tob_staging_fifo_resets_reg: entity work.ipbus_reg_v
719  port map(
720  clk => ipb_clk,
721  reset => stage_fifo_rst_rst,
722  ipbus_in => ipbw(N_SLV_Tob_staging_fifo_resets),
723  ipbus_out => ipbr(N_SLV_Tob_staging_fifo_resets),
724  stb(0) => stage_fifo_rst_stb,
725  q(0) => stage_fifo_reset_bits
726  );
727 stage_fifo_rst_rst <= stage_fifo_rst_stb or ipb_rst;
728 stage_fifo_reset <= stage_fifo_reset_bits(0);
729 stage_busy_thresh_reset <= stage_fifo_reset_bits(2);
730 stage_xoff_thresh_reset <= stage_fifo_reset_bits(3);
731 stage_watermark_reset <= stage_fifo_reset_bits(1);
732 flx_bp_count_reset <= stage_fifo_reset_bits(4);
733 
734 
735 
736 --Tob_staging_fifo_status
737 Tob_stage_fifo_status_reg : entity work.ipbus_syncreg_v
738  generic map (
739  N_CTRL => 0,
740  N_STAT => 1
741  )
742  port map (
743  clk => ipb_clk,
744  rst => ipb_rst,
745  ipb_in => ipbw(N_SLV_Tob_staging_fifo_status),
746  ipb_out => ipbr(N_SLV_Tob_staging_fifo_status),
747  slv_clk => pp_clock,
748  d(0) => Stage_fifo_status,
749  qmask => (others => (others => '1')),
750  stb => open,
751  rstb => open
752  );
753 
754 stage_fifo_status(0) <= stage_fifo_full;
755 stage_fifo_status(1) <= Stage_fifo_busy_i;
756 stage_fifo_status(2) <= Stage_fifo_xoff_i;
757 stage_fifo_status(31 downto 3) <= (others => '0');
758 
759 --Tob_staging_fifo_busy_Count
760 
761 Tob_stage_busy_Count_reg : entity work.ipbus_syncreg_v
762  generic map (
763  N_CTRL => 0,
764  N_STAT => 1
765  )
766  port map (
767  clk => ipb_clk,
768  rst => ipb_rst,
769  ipb_in => ipbw(N_SLV_Tob_staging_fifo_busy_Count),
770  ipb_out => ipbr(N_SLV_Tob_staging_fifo_busy_Count),
771  slv_clk => rt_clk, --pp_clock,
772  d(0) => Stage_fifo_busy_count,
773  qmask => (others => (others => '1')),
774  stb => open,
775  rstb => open
776  );
777 
778 
779 --Tob_staging_fifo_xoff_Count
780 Tob_stage_xoff_Count_reg : entity work.ipbus_syncreg_v
781  generic map (
782  N_CTRL => 0,
783  N_STAT => 1
784  )
785  port map (
786  clk => ipb_clk,
787  rst => ipb_rst,
788  ipb_in => ipbw(N_SLV_Tob_staging_fifo_xoff_Count),
789  ipb_out => ipbr(N_SLV_Tob_staging_fifo_xoff_Count),
790  slv_clk => rt_clk, --pp_clock,
791  d(0) => Stage_fifo_xoff_count,
792  qmask => (others => (others => '1')),
793  stb => open,
794  rstb => open
795  );
796 
797 
798 
799 --Note: this must be mapped to an even address (addr(0) = '0') and the following address left blank
800 Tob_timeout_reg : entity work.ipbus_ctrlreg_v
801  generic map (
802  N_CTRL => 1,
803  N_STAT => 1
804  )
805  port map (
806  clk => ipb_clk,
807  reset => ipb_rst, --load_defaults, --for some reason the register is being set to 0 on proc reset.
808  ipbus_in => ipbw(N_SLV_TOB_TIMEOUT_VALUES),
809  ipbus_out => ipbr(N_SLV_TOB_TIMEOUT_VALUES),
810  -- slv_clk => load_init_value,
811  ctrl_default(0) => timeout_defaults,
812  d(0) => timeout_defaults, --(others => '0'),
813  q(0) => tob_timeouts,
814  -- qmask => (others => (others => '1')),
815  stb => open
816 -- rstb => open
817  );
818 
819 load_defaults <= ipb_rst or reset;
820 timeout_1_val <= tob_timeouts(15 downto 0);
821 --timeout_1_val <= timeout_1_default;
822 timeout_n_val <= tob_timeouts(31 downto 16);
823 --timeout_n_val <= timeout_n_default;
824 timeout_defaults <= timeout_n_default & timeout_1_default;
825 
826 
827 --timeout_reg_ila : default_reg_ila
828 --PORT MAP (
829 --clk => ipb_clk,
830 -- probe0 => timeout_defaults, --32
831 -- probe1 => tob_timeouts, --32
832 -- probe2(0) => ipb_rst,
833 -- probe3(0) => reset
834 --);
835 
836 
837 
838 --initialise the timing constants
839 --process (pp_clock) begin
840 -- if rising_edge (pp_clock) then
841 -- if reset = '1' then
842 -- load_init_value <= '1';
843 -- else
844 -- load_init_value <= '0';
845 -- end if;
846 -- end if;
847 --end process;
848 
849 error_count_register : entity work.ipbus_syncreg_v
850  generic map (
851  N_CTRL => 0,
852  N_STAT => 1
853  )
854  port map (
855  clk => ipb_clk,
856  rst => ipb_rst,
857  ipb_in => ipbw(N_SLV_tob_error_count),
858  ipb_out => ipbr(N_SLV_Tob_error_count),
859  slv_clk => pp_clock,
860  d(0) => (BCN_cnt & bad_l1id_cnt & crc20_cnt & crc9_cnt),
861  qmask => (others => (others => '1')),
862  stb => open,
863  rstb => open
864  );
865 
866 clr_crc9_cnt <= ipb_rst or reset or tob_proc_reg_reset(0);
867 clr_crc20_cnt <= ipb_rst or reset or tob_proc_reg_reset(1);
868 clr_l1id_cnt <= ipb_rst or reset or tob_proc_reg_reset(2);
869 clr_bcn_cnt <= ipb_rst or reset or tob_proc_reg_reset(3);
870 
871 clr_timeout_err <= ipb_rst or reset or tob_proc_reg_reset(5);
872 clr_event_timer <= ipb_rst or reset or tob_proc_reg_reset(6);
873 
874 clr_pkt_wait_timer <= ipb_rst or reset or tob_proc_reg_reset(8);
875 clr_max_timeout <= ipb_rst or reset or tob_proc_reg_reset(9);
876 
877 tob_proc_reset_reg :entity work.ipbus_reg_v
878  port map(
879  clk => ipb_clk,
880  reset => tob_proc_rst_rst,
881  ipbus_in => ipbw(N_SLV_tob_error_reset),
882  ipbus_out => ipbr(N_SLV_tob_error_reset),
883  stb(0) => tob_proc_rst_stb,
884  q(0) => tob_proc_reg_reset
885  );
886 tob_proc_rst_rst <= tob_proc_rst_stb or ipb_rst;
887 
888 
889 
890 packet_capture : pkt_capture_regs
891 
892  Port map (
893 
894  ipb_clk => ipb_clk,
895  ipb_rst => ipb_rst,
896  ipb_in => ipbw(N_SLV_PKT_CAPTURE_REGS),
897 -- ipb_out => ipb_rbus,
898  ipb_out => ipbr(N_SLV_PKT_CAPTURE_REGS),
899  pp_clock => pp_clock,
900  full_mode_stat => full_mode_stat,
901  m_tdata => m_tdata,
902  m_tvalid => m_tvalid,
903  m_tlast => m_tlast,
904  m_header_marker => m_header_marker
905 
906  );
907 
908 input_capture : input_capture_regs
909 
910  Port map (
911 
912  ipb_clk => ipb_clk,
913  ipb_rst => ipb_rst,
914  ipb_in => ipbw(N_SLV_INPUT_CAPTURE_REGS),
915  ipb_out => ipbr(N_SLV_INPUT_CAPTURE_REGS),
916  pp_clock => pp_clock,
917  current_chan => current_chan(4 downto 0),
918  s_tdata => s_tdata,
919  s_tvalid => s_tvalid,
920  s_tlast => s_tlast,
921  s_header_mark => s_header_mark,
922  poll_chan => poll_chan,
923  timeout_err => timeout_err
924 
925  );
926 
927 
928 
929 
930 
931 
932 
933 
934 -----WATCHDOG TIMER CONTROLS-------
935 
936 watchdog_control_reg: entity work.ipbus_reg_v
937  port map(
938  clk => ipb_clk,
939  reset => ipb_rst,
940  ipbus_in => ipbw(N_SLV_watchdog_control),
941  ipbus_out => ipbr(N_SLV_watchdog_control),
942  q(0) => watchdog_control
943  );
944 
945  wdog_disable <= watchdog_control(0);
946  wdog_fifo_reset_en <= watchdog_control(1);
947  l1id_resync_enable <= watchdog_control(4);
948  tob_timeout_1_disable <= watchdog_control(8);
949  tob_timeout_n_disable <= watchdog_control(9);
950 
951 --Note: this must be mapped to an even address (addr(0) = '0') and the following address left blank
952 wdog_threshold_reg : entity work.ipbus_ctrlreg_v
953  generic map (
954  N_CTRL => 1,
955  N_STAT => 0
956  )
957  port map (
958  clk => ipb_clk,
959  reset => ipb_rst, --load_defaults, --for some reason the register is being set to 0 on proc reset.
960  ipbus_in => ipbw(N_SLV_WATCHDOG_THRESHOLD_VALUE),
961  ipbus_out => ipbr(N_SLV_WATCHDOG_THRESHOLD_VALUE),
962  -- slv_clk => load_init_value,
963  ctrl_default(0) => watchdog_default,
964  d(0) => watchdog_default,
965  q(0) => wdog_threshold_i,
966  -- qmask => (others => (others => '1')),
967  stb => open
968 -- rstb => open
969  );
970 
971 watchdog_default <= x"0000" & wdog_thresh_default;
972 wdog_threshold <= wdog_threshold_i(15 downto 0);
973 clr_wdog_cnt <= tob_proc_reg_reset(4);
974 
975 watchdog_overflow_count_reg : entity work.ipbus_syncreg_v
976  generic map (
977  N_CTRL => 0,
978  N_STAT => 1
979  )
980  port map (
981  clk => ipb_clk,
982  rst => ipb_rst,
983  ipb_in => ipbw(N_SLV_watchdog_overflow_count),
984  ipb_out => ipbr(N_SLV_watchdog_overflow_count),
985  slv_clk => pp_clock,
986  -- d(0) => x"0000" & wdog_overflow_count,
987  d(0) => wdog_overflow_count,
988  qmask => (others => (others => '1')),
989  stb => open,
990  rstb => open
991  );
992 
993 
994 
995 
996 
997 
998 
999 wdog_overflow_counter : edge_error_counter
1000  generic map (
1001  cwidth => 32
1002  )
1003  port map (
1004  -- clock => ipb_clk,
1005  clock => pp_clock,
1006  counter_reset => clr_wdog_cnt,
1007  system_reset => ipb_rst,
1008  error => wdog_overflow,
1009  error_count => wdog_overflow_count
1010  );
1011 
1012 wdog_fifo_reset <= wdog_overflow and wdog_fifo_reset_en and not wdog_disable;
1013 
1014 crc9_error_map_reg : entity work.ipbus_syncreg_v
1015  generic map (
1016  N_CTRL => 0,
1017  N_STAT => 1
1018  )
1019  port map (
1020  clk => ipb_clk,
1021  rst => ipb_rst,
1022  ipb_in => ipbw(N_SLV_crc9_error_map),
1023  ipb_out => ipbr(N_SLV_crc9_error_map),
1024  slv_clk => pp_clock,
1025  d(0) => x"00" & crc9_map ,
1026  qmask => (others => (others => '1')),
1027  stb => open,
1028  rstb => open
1029  );
1030 
1031 crc20_error_map_reg : entity work.ipbus_syncreg_v
1032  generic map (
1033  N_CTRL => 0,
1034  N_STAT => 1
1035  )
1036  port map (
1037  clk => ipb_clk,
1038  rst => ipb_rst,
1039  ipb_in => ipbw(N_SLV_crc20_error_map),
1040  ipb_out => ipbr(N_SLV_crc20_error_map),
1041  slv_clk => pp_clock,
1042  d(0) => x"00" & crc20_map ,
1043  qmask => (others => (others => '1')),
1044  stb => open,
1045  rstb => open
1046  );
1047 
1048 bcn_mismatch_map_reg : entity work.ipbus_syncreg_v
1049  generic map (
1050  N_CTRL => 0,
1051  N_STAT => 1
1052  )
1053  port map (
1054  clk => ipb_clk,
1055  rst => ipb_rst,
1056  ipb_in => ipbw(N_SLV_bcn_mismatch_map),
1057  ipb_out => ipbr(N_SLV_bcn_mismatch_map),
1058  slv_clk => pp_clock,
1059  d(0) => x"00" & bcn_map ,
1060  qmask => (others => (others => '1')),
1061  stb => open,
1062  rstb => open
1063  );
1064 
1065 l1id_mismatch_map_reg : entity work.ipbus_syncreg_v
1066  generic map (
1067  N_CTRL => 0,
1068  N_STAT => 1
1069  )
1070  port map (
1071  clk => ipb_clk,
1072  rst => ipb_rst,
1073  ipb_in => ipbw(N_SLV_l1id_mismatch_map),
1074  ipb_out => ipbr(N_SLV_l1id_mismatch_map),
1075  slv_clk => pp_clock,
1076  d(0) => x"00" & l1id_map ,
1077  qmask => (others => (others => '1')),
1078  stb => open,
1079  rstb => open
1080  );
1081 
1082 
1083 timeout_error_map_reg : entity work.ipbus_syncreg_v
1084  generic map (
1085  N_CTRL => 0,
1086  N_STAT => 1
1087  )
1088  port map (
1089  clk => ipb_clk,
1090  rst => ipb_rst,
1091  ipb_in => ipbw(N_SLV_timeout_error_map),
1092  ipb_out => ipbr(N_SLV_timeout_error_map),
1093  slv_clk => pp_clock,
1094  d(0) => x"00" & timeout_map ,
1095  qmask => (others => (others => '1')),
1096  stb => open,
1097  rstb => open
1098  );
1099 
1100 
1101 
1102 --make sure mapper reset inputs are glitchless by registering outside of the ipbus reg
1103 process (ipb_clk) begin
1104  if rising_edge (ipb_clk) then
1105  clr_crc9_cnt_s <= clr_crc9_cnt;
1106  clr_crc20_cnt_s <= clr_crc20_cnt;
1107  clr_BCN_cnt_s <= clr_BCN_cnt;
1108  clr_l1id_cnt_s <= clr_l1id_cnt;
1109  clr_timeout_s <= clr_timeout_err;
1110  end if;
1111 end process;
1112 
1113 chan_error_mapper : chan_err_map
1114  Port map (
1115  clock => pp_clock,
1116  reset_0 => clr_crc9_cnt_s,
1117  reset_1 => clr_crc20_cnt_s,
1118  reset_2 => clr_BCN_cnt_s,
1119  reset_3 => clr_l1id_cnt_s,
1120  reset_4 => clr_timeout_s,
1121  error_0 => crc9_err,
1122  error_1 => crc20_err,
1123  error_2 => BCID_mismatch,
1124  error_3 => L1ID_mismatch,
1125  error_4 => timeout_err,
1126  sample_0 => '1',
1127  sample_1 => '1',
1128  sample_2 => '1',
1129  sample_3 => '1',
1130  sample_4 => '1',
1131  chan_in => current_chan(4 downto 0),
1132  error_map_0 => crc9_map,
1133  error_map_1 => crc20_map,
1134  error_map_2 => bcn_map,
1135  error_map_3 => l1id_map,
1136  error_map_4 => timeout_map
1137  );
1138 
1139 
1140 
1141 
1142 avg_event_time_reg : entity work.ipbus_syncreg_v
1143  generic map (
1144  N_CTRL => 0,
1145  N_STAT => 1
1146  )
1147  port map (
1148  clk => ipb_clk,
1149  rst => ipb_rst,
1150  ipb_in => ipbw(N_SLV_average_event_time),
1151  ipb_out => ipbr(N_SLV_average_event_time),
1152  slv_clk => pp_clock,
1153  d(0) => x"0000" & avg_event_time ,
1154  qmask => (others => (others => '1')),
1155  stb => open,
1156  rstb => open
1157  );
1158 
1159 event_time_reg : entity work.ipbus_syncreg_v
1160  generic map (
1161  N_CTRL => 0,
1162  N_STAT => 1
1163  )
1164  port map (
1165  clk => ipb_clk,
1166  rst => ipb_rst,
1167  ipb_in => ipbw(N_SLV_event_time),
1168  ipb_out => ipbr(N_SLV_event_time),
1169  slv_clk => pp_clock,
1170 -- d(0) => "0000" & max_event_time & "0000" & event_time,
1171  d(0) => max_event_time & event_time ,
1172  qmask => (others => (others => '1')),
1173  stb => open,
1174  rstb => open
1175  );
1176 
1177 dbg_pkt_count_reg : entity work.ipbus_syncreg_v
1178  generic map (
1179  N_CTRL => 0,
1180  N_STAT => 1
1181  )
1182  port map (
1183  clk => ipb_clk,
1184  rst => ipb_rst,
1185  ipb_in => ipbw(N_SLV_debug_packet_count),
1186  ipb_out => ipbr(N_SLV_debug_packet_count),
1187  slv_clk => pp_clock,
1188  d(0) => dbg_pkt_count,
1189  qmask => (others => (others => '1')),
1190  stb => open,
1191  rstb => open
1192  );
1193 
1194  dbg_pkt_count_reset <= tob_proc_reg_reset(7);
1195 
1196  flx_bp_time_reg : entity work.ipbus_syncreg_v
1197  generic map (
1198  N_CTRL => 0,
1199  N_STAT => 1
1200  )
1201  port map (
1202  clk => ipb_clk,
1203  rst => ipb_rst,
1204  ipb_in => ipbw(N_SLV_FELIX_BACKPRESSURE_TIME),
1205  ipb_out => ipbr(N_SLV_FELIX_BACKPRESSURE_TIME),
1206  slv_clk => rt_clk, --pp_clock,
1207  d(0) => flx_bp_time,
1208  qmask => (others => (others => '1')),
1209  stb => open,
1210  rstb => open
1211  );
1212 
1213 --------felix backpressure selection mux -------
1214 
1215 with full_mode_ctrl_i (11 downto 8) select
1216  flx_backpressure_raw <= flx_backpressure(0) when x"0",
1217  flx_backpressure(1) when x"1",
1218  flx_backpressure(2) when x"2",
1219  flx_backpressure(3) when x"3",
1220  flx_backpressure(4) when x"4",
1221  flx_backpressure(5) when x"5",
1222  flx_backpressure(6) when x"6",
1223  flx_backpressure(7) when x"7",
1224  flx_backpressure(8) when x"8",
1225  flx_backpressure(9) when x"9",
1226  flx_backpressure(10) when x"A",
1227  flx_backpressure(11) when x"B",
1228  '0' when others;
1229 
1230 flx_bp_enable <= full_mode_ctrl_i(4);
1231 
1232 --resync felix backpressure to pp_clock for use in processor
1233 process (pp_clock)
1234  begin
1235  if rising_edge (pp_clock) then
1236  flx_backpressure_bit <= flx_backpressure_raw;
1237  end if;
1238 end process;
1239 
1240 --resync felix backpressure to rt_clock for counting time
1241 process (rt_clk)
1242  begin
1243  if rising_edge (rt_clk) then
1244  flx_backpressure_rt <= flx_backpressure_raw;
1245  end if;
1246 end process;
1247 
1248 process(rt_clk, ipb_rst, flx_bp_count_reset)
1249  begin
1250  if (ipb_rst or flx_bp_count_reset) = '1' then -- async (p)reset -> put 'reset in sensitivity list
1251  flx_bp_time <= (others => '0');
1252  elsif rising_edge(rt_clk) then
1253  if ((flx_bp_enable and flx_backpressure_rt) = '1') and (flx_bp_time < x"ffffffff") then
1254  flx_bp_time <= (flx_bp_time + 1);
1255  else
1256  flx_bp_time <= flx_bp_time;
1257  end if;
1258  end if;
1259  end process;
1260 
1261  pkt_wait_time_last_reg : entity work.ipbus_syncreg_v
1262  generic map (
1263  N_CTRL => 0,
1264  N_STAT => 1
1265  )
1266  port map (
1267  clk => ipb_clk,
1268  rst => ipb_rst,
1269  ipb_in => ipbw(N_SLV_PACKET_WAIT_TIME_LAST),
1270  ipb_out => ipbr(N_SLV_PACKET_WAIT_TIME_LAST),
1271  slv_clk => pp_clock,
1272  d(0) => l1id_measure_last,
1273  qmask => (others => (others => '1')),
1274  stb => open,
1275  rstb => open
1276  );
1277 
1278 pkt_wait_time_max_reg : entity work.ipbus_syncreg_v
1279  generic map (
1280  N_CTRL => 0,
1281  N_STAT => 1
1282  )
1283  port map (
1284  clk => ipb_clk,
1285  rst => ipb_rst,
1286  ipb_in => ipbw(N_SLV_PACKET_WAIT_TIME_MAX),
1287  ipb_out => ipbr(N_SLV_PACKET_WAIT_TIME_MAX),
1288  slv_clk => pp_clock,
1289  d(0) => l1id_measure_max,
1290  qmask => (others => (others => '1')),
1291  stb => open,
1292  rstb => open
1293  );
1294 
1295 pkt_max_wait_time_L1id_reg : entity work.ipbus_syncreg_v
1296  generic map (
1297  N_CTRL => 0,
1298  N_STAT => 1
1299  )
1300  port map (
1301  clk => ipb_clk,
1302  rst => ipb_rst,
1303  ipb_in => ipbw(N_SLV_PACKET_MAX_WAIT_TIME_L1ID),
1304  ipb_out => ipbr(N_SLV_PACKET_MAX_WAIT_TIME_L1ID),
1305  slv_clk => pp_clock,
1306  d(0) => l1id_max_l1id,
1307  qmask => (others => (others => '1')),
1308  stb => open,
1309  rstb => open
1310  );
1311 
1312 
1313  max_timeout_reg : entity work.ipbus_syncreg_v
1314  generic map (
1315  N_CTRL => 0,
1316  N_STAT => 1
1317  )
1318  port map (
1319  clk => ipb_clk,
1320  rst => ipb_rst,
1321  ipb_in => ipbw(N_SLV_MAX_TIMEOUT),
1322  ipb_out => ipbr(N_SLV_MAX_TIMEOUT),
1323  slv_clk => pp_clock,
1324  d(0) => max_timeout_and_chan,
1325  qmask => (others => (others => '1')),
1326  stb => open,
1327  rstb => open
1328  );
1329 
1330 max_timeout_and_chan(15 downto 0) <= timeout_counter_max;
1331 max_timeout_and_chan(23 downto 16) <= "000" & max_chan;
1332 max_timeout_and_chan(31 downto 24) <= x"00";
1333 
1334 event_proc_timer : event_timer
1335  generic map (
1336  start_state => x"12", --read_ttc x"02", --start_reading
1337  stop_state => x"11" --wait for event
1338  )
1339 
1340  Port map (
1341  clock => pp_clock,
1342  reset => clr_event_timer,
1343  current_state => current_state,
1344 
1345 
1346  event_time => event_time,
1347  watermark => max_event_time,
1348  avg_time => avg_event_time
1349  );
1350 
1351 trace_input(7 downto 0) <= current_chan;
1352 trace_input(8) <= wdog_overflow;
1353 trace_input(9) <= timeout_err;
1354 trace_input(10) <= l1id_mismatch;
1355 trace_input(11) <= s_tvalid;
1356 trace_input(12) <= header_fifo_valid;
1357 trace_input(13) <= header_mark;
1358 trace_input(14) <= hdr_crc_error;
1359 trace_input(15) <= ttc_crc_error;
1360 
1361 trace_module : Processor_trace_module
1362  generic map(
1363  ADDR_WIDTH => 8,
1364  DATA_WIDTH => 32
1365  )
1366  Port map(
1367  ipb_clk => ipb_clk,
1368  ipb_rst => ipb_rst,
1369  ipb_in => ipbw(N_SLV_PROC_TRACE),
1370  ipb_out => ipbr(N_SLV_PROC_TRACE),
1371  pp_clock => pp_clock,
1372  reset => reset,
1373  trace_input => trace_input,
1374  state => current_state,
1375  wd_event => wdog_overflow, --watchdog overflow signal
1376  timeout_error => timeout_err
1377 );
1378 
1379 
1380 
1381 
1382 
1383 
1384 
1385 
1386 
1387 
1388 end generate no_sim_regs;
1389 
1390 l1id_capt: l1id_capture
1391  generic map(
1392  sim => sim
1393  )
1394  Port map(
1395  ipb_clk => ipb_clk,
1396  ipb_rst => ipb_rst,
1397  ipb_in => ipbw(N_SLV_L1ID_CAPTURE_REGS),
1398  ipb_out => ipbr(N_SLV_L1ID_CAPTURE_REGS),
1399  pp_clock => pp_clock,
1400  reset => reset,
1401  s_tvalid => s_tvalid,
1402  s_tlast => s_tlast,
1403  idle_state => idle_status,--note that poll_chan could be used as the sampling point thus eliminating the need to s_tvalid, s_tlast, and idle_status
1404  l1id_ttc => L1ID_ttc_32_reg,
1405  l1id_pkt => s_tdata(63 downto 32),
1406  current_chan => current_chan,
1407  first_chan => first_chan,
1408  poll_chan => poll_chan
1409  );
1410 
1411 idle_status <= '1' when (current_state = 5x"00") else '0';
1412 --L1ID <= master_header(35 downto 12);
1413 --ECRID <= master_header(43 downto 36);
1414 --l1id_ttc <= (ECRID & L1ID);
1415 --l1id_ttc <= L1ID_ttc_32_reg;
1416 --end generate no_sim_regs;
1417 
1418 -->crc counters
1419 process (pp_clock) begin
1420  if rising_edge (pp_clock) then
1421  if clr_crc20_cnt = '1' then
1422  crc20_cnt <= x"00";
1423  elsif (crc20_err = '1') and (crc20_cnt < x"FF") then
1424  crc20_cnt <= crc20_cnt + 1;
1425  else
1426  crc20_cnt <= crc20_cnt;
1427  end if;
1428  end if;
1429 end process;
1430 
1431 
1432 
1433 process (pp_clock) begin
1434  if rising_edge (pp_clock) then
1435  if clr_crc9_cnt = '1' then
1436  crc9_cnt <= x"00";
1437  elsif (crc9_err = '1') and (crc9_cnt < x"FF")then
1438  crc9_cnt <= crc9_cnt + 1;
1439  else
1440  crc9_cnt <= crc9_cnt;
1441  end if;
1442  end if;
1443 end process;
1444 
1445 
1446 ----BCID mismatch counter
1447 
1448 process (pp_clock) begin
1449  if rising_edge (pp_clock) then
1450  if clr_BCN_cnt = '1' then
1451  BCN_cnt <= x"00";
1452  elsif (BCID_mismatch = '1') and (BCN_cnt < x"FF")then
1453  BCN_cnt <= BCN_cnt + 1;
1454  else
1455  BCN_cnt <= BCN_cnt;
1456  end if;
1457  end if;
1458 end process;
1459 
1460 ----L1ID mismatch counter
1461 
1462 process (pp_clock) begin
1463  if rising_edge (pp_clock) then
1464  if clr_l1id_cnt = '1' then
1465  bad_l1id_cnt <= x"00";
1466  elsif (L1ID_mismatch = '1') and (bad_l1id_cnt < x"FF")then
1467  bad_l1id_cnt <= bad_l1id_cnt + 1;
1468  else
1469  bad_l1id_cnt <= bad_l1id_cnt;
1470  end if;
1471  end if;
1472 end process;
1473 
1474 
1475 
1476 
1477 
1478 
1479 sim_only: if SIM=1 generate
1480  wdog_fifo_reset <= '0';
1481 end generate sim_only;
1482 
1483 tob_stage_busy_counter: entity work.threshold_counter
1484  port map (
1485  clock => rt_clk, --pp_clock,
1486  reset => stage_busy_thresh_reset,
1487  threshold => tob_stage_busy_thresh,
1488  level => stage_fifo_level,
1489  above_count => stage_fifo_busy_count,
1490  busy => open --stage_fifo_busy_i
1491  );
1492 
1493  tob_stage_busy_flag: entity work.threshold_counter
1494  port map (
1495  clock => pp_clock, --pp_clock,
1496  reset => stage_busy_thresh_reset,
1497  threshold => tob_stage_busy_thresh,
1498  level => stage_fifo_level,
1499  above_count => open, --stage_fifo_busy_count,
1500  busy => stage_fifo_busy_sync
1501  );
1502 
1503  --stage_fifo_busy <= (stage_fifo_busy_i and busy_enable) or force_busy;
1504 
1505 stage_fifo_busy_i <= (stage_fifo_busy_sync and busy_enable) or force_busy;
1506 stage_fifo_busy <= stage_fifo_busy_i;
1507 
1508  tob_stage_xoff_counter: entity work.threshold_counter
1509  port map (
1510  clock => rt_clk, --pp_clock,
1511  reset => stage_xoff_thresh_reset,
1512  threshold => tob_stage_xoff_thresh,
1513  level => stage_fifo_level,
1514  above_count => stage_fifo_xoff_count,
1515  busy => open --stage_fifo_xoff_i
1516  );
1517 
1518 tob_stage_xoff_flag: entity work.threshold_counter
1519  port map (
1520  clock => pp_clock, --pp_clock,
1521  reset => stage_xoff_thresh_reset,
1522  threshold => tob_stage_xoff_thresh,
1523  level => stage_fifo_level,
1524  above_count => open, --stage_fifo_xoff_count,
1525  busy => stage_fifo_xoff_sync
1526  );
1527 
1528 
1529 --stage_fifo_xoff <= stage_fifo_xoff_i and xoff_enable;
1530 stage_fifo_xoff_i <= stage_fifo_xoff_sync and xoff_enable;
1531 stage_fifo_xoff <= stage_fifo_xoff_i;
1532 
1533 
1534 xoff_condition <= '1' when ((stage_fifo_xoff_i = '1') and (tob_stage_xoff_thresh /= x"0000")) else '0';
1535 busy_condition <= '1' when ((stage_fifo_busy_i = '1') and (tob_stage_busy_thresh /= x"0000")) else '0';
1536 
1537 stop_proc <= xoff_condition or busy_condition;
1538 
1539 
1540 ------local pointer to "current_chan" created to ease routing from current chan generated in the input mux
1541 
1542 process (pp_clock) begin
1543  if rising_edge (pp_clock) then
1544  if ((reset = '1') or (chan_pointer_reset = '1')) then
1545  chan_count <= first_chan;
1546  elsif (nxt_chan_0 = '1') then
1547  if (chan_count = last_chan) then
1548  chan_count <= first_chan;
1549  else
1550  chan_count <= chan_count + '1';
1551  end if;
1552  else
1553  chan_count <= chan_count;
1554  end if;
1555  end if;
1556  end process;
1557 
1558 current_chan(4 downto 0) <= chan_count;
1559 current_chan(7 downto 5) <= (others => '0');
1560 
1561 
1562 
1563 end RTL;
Processor_trace_module
Definition: Processor_trace_module.vhd:29
chan_err_map
Definition: chan_err_map.vhd:34
edge_error_counter
Definition: edge_error_counter.vhd:38
event_timer
Definition: event_timer.vhd:35
input_capture_regs
Definition: input_capture_regs.vhd:18
l1id_capture
Definition: l1id_capture.vhd:38
pkt_capture_regs
Definition: pkt_capture_regs.vhd:18
threshold_counter
Definition: threshold_counter.vhd:29
tob_proc_regs.RTL
Definition: tob_proc_regs.vhd:124
tob_proc_regs
Definition: tob_proc_regs.vhd:37
Generated on Sat Dec 14 2024 13:33:14 for ROD firmware by   doxygen 1.9.1